DLA SMD-5962-89468 REV C-2007 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASEABLE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《硅单片紫外线擦写的可编程逻辑阵列互补型金属氧化物半导体数字存储微电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added 3 devices, 02 - 04. Updated format, editorial change throughout. 94-10-24 M. A. Frye B Add 05 device, update format, editorial changes throughout. 97-02-26 Ray Monnin C Boilerplate update, part of 5 year review. ksr 07-03-23 Robert M. Heber

2、 REV SHET REV C C C C C SHEET 15 16 17 18 19 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth S. Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.dscc.

3、dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-03-27 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, UV ERASEABLE PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON AMSC N/A REVISION LEVEL C SIZE A CAGE CODE

4、67268 5962-89468 SHEET 1 OF 19 DSCC FORM 2233 APR 97 5962-E311-07 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89468 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC

5、FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89468 01 X A

6、Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 1/ Circuit function Propagation Delay 01 128-Macrocell EPLD 35 ns 02 128-Macrocell EPLD 30 ns 03 128-Macr

7、ocell EPLD 25 ns 04 128-Macrocell EPLD 20 ns 05 128-Macrocell EPLD 15 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA15-PN 68 pin grid array package 2/ Y GQCC1-J68 68 J-leaded chip ca

8、rrier 2/ Z See figure 1 68 quad flat package 2/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage to ground potential - 2.0 V dc to +7.0 V dc DC Input voltage- 2.0 V dc to +7.0 V dc Maximum power dissipation 3/ - 2.5 W Lead

9、temperature (soldering, 10 seconds)- +260C Thermal resistance, junction-to-case (JC): Case outlines X and Y- See MIl-STD-1835 Case outline Z - 10C/W 4/ Junction temperature (TJ) - +175C Storage temperature range - -65C to +150C Temperature under bias - -55C to +125C Endurance- 25 erase/write cycles

10、(minimum) Data retention - 10 years minimum 1.4 Recommended operating conditions. Supply voltage (VCC) - +4.5 V dc to +5.5 V dc Ground voltage (GND) - 0 V dc Input high voltage (VIH) - 2.2 V dc minimum Input low voltage (VIL) - 0.8 V dc maximum Case operating temperature range (TC) - -55C to +125C 1

11、 Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and will also be listed in MIL-HDBK-103. 2/ Lid shall be transparent to permit ultraviolet light erasure. 3/ Must withstand the added PDdue to short circuit test (e.g., ISC). 4/ When

12、 the thermal resistance for this case is specified in MIL-STD-1835 that value shall supersede the value indicated herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89468 DEFENSE SUPPLY CENTER COLUMBUS C

13、OLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the is

14、sues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Stand

15、ard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from

16、 the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however,

17、 supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this dr

18、awing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity

19、approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A

20、 “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case o

21、utline(s). The case outline(s) shall be in accordance with figure 1 and 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. The truth table shall be as specified on figure 3. 3.2.3.1 Unprogrammed devices. The truth table for unprog

22、rammed devices for contracts involving no altered item drawing shall be as specified on figure 3. When required in groups A, B, or C (see 4.3), the devices shall be programmed by the manufacturer prior to test with a minimum of 50 percent of the total number of gates programmed or to any altered ite

23、m drawing pattern which includes at least 25 percent of the total number of gates programmed. 3.2.3.2 Programmed devices. The truth tables for programmed devices shall be as specified by an attached altered item drawing. 3.3 Electrical performance characteristics. Unless otherwise specified herein,

24、the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described

25、 in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89468 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance chara

26、cteristics. Conditions Limits Test Symbol -55CTC+125C Group A Device Unit 4.5V VCC 5.5V subgroups types Min Max unless otherwise specified Output high voltage VOH VCC= 4.5 V, VIH= 2.2 V, 1, 2, 3 All 2.4 V IOH= -4.0 mA, VIL= 0.8 V Output low voltage VOL VCC= 4.5 V, VIH= 2.2 V, 1, 2, 3 All 0.45 V IOL=

27、 8.0 mA, VIL= 0.8 V Input high voltage VIH 1, 2, 3 All 2.2 V 1/ 2/ Input low voltage VIL 1, 2, 3 All 0.8 V 1/ 2/ Input leakage IIX VCC= 5.5 V, 1, 2, 3 All -10 10 uA current VIN= 5.5 V and GND Output leakage IOZ VCC= 5.5 V, 1, 2, 3 All -40 40 uA current VOUT= 5.5 V and GND Output short circuit ISC VC

28、C= 5.5 V, 1, 2, 3 All -30 -90 mA current 2/ 3/ VOUT= 0.5 V Power supply current ICC1 VCC= 5.5 V, IOUT= 0 mA, 1, 2, 3 All 700 mA 2/ 4/ VIN= VCCto GND, f = 1/tPD1 Power supply current 4/ ICC2 VCC= 5.5 V, IOUT= 0 mA, 1, 2, 3 All 300 mA (Standby) VIN= GND Input capacitance 2/ CIN VCC= 5.0 V, VIN= 0.0 V,

29、 4 All 10 pF TA= 25C, f = 1MHz (see 4.3.1c) Output capacitance 2/ COUT VCC= 5.0 V, VOUT= 0.0 V, 4 All 20 pF TA= 25C, f = 1MHz (see 4.3.1c) Functional tests See 4.3.1d 7,8A,8B All See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

30、IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89468 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Conditions Limits Test Symbol -55CTC+125C Group A Device Unit 4.5V VCC 5.5V sub

31、groups types Min Max unless otherwise specified External Synchronous Switching Characteristics Dedicated input to See figure 5 5/ 01 35 combinatorial output tPD1 9, 10, 11 02 30 ns delay 6/ 03 25 04 20 05 15 I/O input to combinatorial tPD2 9, 10, 11 01 55 ns output delay 7/ 02 46 03 40 04 33 05 25 D

32、edicated input to 01 55 ns combinatorial output tPD3 9, 10, 11 02 44 delay with expander 03 37 delay 2/ 8/ 04 30 05 23 I/O input to combinatorial tPD4 9, 10, 11 01 75 ns output delay with 02 60 expander delay 2/ 9/ 03 51 04 43 05 33 Input to output enable tEA 9, 10, 11 01 35 ns delay 2/ 6/ 02 30 03

33、25 04 20 05 15 Input to output disable tER 9, 10, 11 01 35 ns delay 2/ 6/ 10/ 02 30 03 25 04 20 05 15 Synchronous clock input tCO1 9, 10, 11 01 20 ns to output delay 02 16 03 14 04 8 05 7 2/ 11/ Synchronous clock to tCO2 9, 10, 11 01 42 ns local feedback to 02 35 combinatorial output 03 30 04 22 05

34、17 6/ 13/ Dedicated input or tS1 9, 10, 11 01 25 ns feedback setup time to 02 20 synchronous clock input 03 15 04 13 05 10 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89468

35、DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Conditions Limits Test Symbol -55CTC+125C Group A Device Unit 4.5V VCC 5.5V subgroups types Min Max unless otherwise specified I/O inpu

36、t setup time to tS2 See figure 5 5/ 9, 10, 11 01 45 ns synchronous clock input 02 36 03 29 2/ 6/ 04 26 05 20 Input hold time from 6/ tH 9, 10, 11 All 0 ns synchronous clock input Synchronous clock input tWH 9, 10, 11 01 12.5 ns high time 02 10 2/ 03 8 04 7 05 5 Synchronous clock input tWL 9, 10, 11 01 12.5 ns low time 02 10 2/ 03 8 04 7 05 5 Asynchronous clear width tRW 9, 10, 11 01 35 ns 2/ 6/ 12/ 02 30 03 25 04 22 05 15 Asynchronous clear tRR 9, 10, 11 01 35 ns recovery time 2/ 6/ 12/ 02