DLA SMD-5962-89469 REV C-2011 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASABLE PROGRAMMABLE LOGIC DEVICE MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R160-93 93-05-12 Michael Frye B Changes in accordance with NOR 5962-R147-94 94-04-21 Michael Frye C Updated for 5 year review - lhl 11-07-11 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN R

2、EPLACED. REV SHEET REV SHEET REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rajesh Pithadia DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL

3、DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Kenneth Rice APPROVED BY Michael Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS UV ERASABLE PROGRAMMABLE LOGIC DEVICE, MONOLITHIC SILICON DRAWING APPROVAL DATE 93-03-25 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-89469 SHEET 1 OF 1

4、4 DSCC FORM 2233 APR 97 5962-E398-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89469 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. Th

5、is drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89469 01 X A Drawing number Device type (see 1.2.1)

6、Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Propagation delay 01 EP1810 2100 gate UV EPLD 45 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-

7、1835 and as follows: Outline letter Descriptive designator Terminals Package style X GQCC1-J68 68 “J” lead chip carrier package 1/ Y CMGA15-P68 68 Pin grid array package 1/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 2/ Supply voltag

8、e range (VCC) . -0.5 V dc to +7.0 V dc DC Input voltage range. -0.5 V dc to VCC+0.5V dc Maximum power dissipation. 2 W 3/ Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC): Case outlines X and Y See MIL-STD-1835 Junction temperature (TJ). +175C Storage temperat

9、ure range. -65C to +150C Temperature under bias range -55C to +125C Endurance 25 erase/write cycles (minimum) Data retention 10 years (minimum) 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Ground voltage (GND) 0 V dc Input high voltage (VIH) 2.0 V dc minimu

10、m Input low voltage (VIL) . 0.8 V dc maximum Case operating temperature range (TC) -55C to +125C _ 1/ Lid shall be transparent to permit ultraviolet light erasure, 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may deg

11、rade performance and affect reliability. 3/ Must withstand the added PDdue to short circuit test (e.g., IOS). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89469 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3

12、990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documen

13、ts are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Compon

14、ent Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Rob

15、bins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unles

16、s a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacture

17、r Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This Q

18、ML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance wi

19、th MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accord

20、ance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item d

21、rawing shall be as specified on figure 2. When required in screening (see 4.2 herein) or qualification conformance inspection, groups A, B, C or D (see 4.3), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of the total number of cells shall be programmed or

22、 at least 25 percent of the total number of cells to any altered item drawing. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical p

23、erformance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Pro

24、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89469 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol C

25、onditions 1/ -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Input leakage current IIVIN= VCC or GND (at VCC= VCCmax) 1, 2, 3 All -10 +10 A Three-state output off current IOZVOUT= VCC or GND (at VCC= VCCmax) 1, 2, 3 All -10 +10 Low level inp

26、ut voltage VIL1, 2, 3 All -0.3 0.8 V High level output voltage VIH1, 2, 3 All 2.0 VCC+ 0.3 Low level output voltage 2/ VOLIOL= +4.0 mA (at VCC= VCCmin), VIH= 3.0 V, VIL= 0.0 V 1, 2, 3 All 0.45 High level TTL output voltage 2/ VOH(TTL)IOH= -4.0 mA (at VCC= VCCmin) 1, 2, 3 All 2.4 High level CMOS outp

27、ut voltage 2/ VOH(CMOS) IOH= -2.0 mA (at VCC= VCCmin), VIH= 3.0 V, VIL= 0.0 V 1, 2, 3 All 3.84 VCCsupply current (standby, non-TURBO) 2/ ICC1VIN = 0 V or VCC1, 2, 3 All 900 A VCCsupply current (active, non-TURBO) 2/ 3/ ICC2VIN = 0 V or VCC, f = 1 MHz 1, 2, 3 All 40 mA VCCsupply current (active, TURB

28、O) 2/ 3/ ICC3VIN = 0 V or VCC, f = fMAX1, 2, 3 All 275 Input capacitance 2/ CINVIN= 0 V dc, f = 1.0 MHz measured from pin to VSSSee 4.3.1c 4 All 20 pF Output capacitance 2/ COUTVOUT= 0 V dc, f = 1.0 MHz measured from pin to VSSSee 4.3.1c 4 All 20 Clock pin capacitance 2/ CCLKVIN= 0 V dc, f = 1.0 MHz

29、 measured from pin to VSSSee 4.3.1c 4 All 25 Clock/VPPpin capacitance 2/ CVPPVOUT= 0 V dc, f = 1.0 MHz measured from pin to VSS See 4.3.1c 4 All 160 Functional tests See 4.3.1d 7, 8 All Input to nonregistered output 4/ 5/ tPD1CL= 35 pF 9, 10, 11 All 45 ns I/O input to nonregistered output 4/ 5/ tPD2

30、9, 10, 11 All 55 Input to output enable 4/ 5/ tPZX9, 10, 11 All 45 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89469 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234

31、 APR 97 See footnotes at end of table. TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Input to output disable 2/ 4/ 5/ tPXZCL= 5 pF Output change = 500 mV

32、9, 10, 11 All 45 ns Asynchronous output clear time 4/ 5/ tCLRCL= 35 pF 9, 10, 11 All 50 I/O input buffer delay 2/ tIO9, 10, 11 All 5 Maximum frequency (1/tSU) 4/ 5/ 6/ 7/ fMAX19, 10, 11 All 33.3 MHz Input setup time 4/ 5/ tSU9, 10, 11 All 30 ns Input hold time 4/ tH9, 10, 11 All 0 Clock high time tC

33、H9, 10, 11 All 15 Clock low time tCL9, 10, 11 All 15 Clock to output delay time 5/ tCO19, 10, 11 All 25 Minimum clock period (tSU+ tCO1) (register output feedback to register input-external path) 8/ tP29, 10, 11 All 55 Minimum clock period (register output feedback to register input-internal path) 5

34、/ tCNT9, 10, 11 All 45 Internal maximum frequency (1/tCNT) 9/ fMAX29, 10, 11 All 22.2 MHz Asynchronous input setup time 4/ 5/ tASU CL= 35 pF 9, 10, 11 All 13 ns Asynchronous input hold time 4/ 5/ tAH 9, 10, 11 All 18 Asynchronous clock low time 4/ 5/ tACL 9, 10, 11 All 18 Asynchronous clock high tim

35、e 4/ 5/ tACH 9, 10, 11 All 18 Asynchronous clock to output delay 4/ 5/ tACO1 9, 10, 11 All 50 Asynchronous minimum clock period (register output feedback to register input-internal path) 5/ 10/ tACNT 9, 10, 11 All 45 Asynchronous internal maximum frequency (1/tACNT) fMAX39, 10, 11 All 22.2 MHz See f

36、ootnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89469 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance c

37、haracteristics Continued. 1/ Screening and characterization of ac delay parameters are conducted at 10 MHz or less. Figure 3 shows the output loading circuit and figure 4 shows the timing diagram. 2/ May not be tested, but shall be guaranteed to the limits specified in table I. 3/ Tested using a dat

38、a pattern specified by the device manufacturer, which has been correlated to four independent 12-bit counters and no output loading. 4/ All array-dependent delays are specified for an XOR pattern. This pattern involves two product terms and two pure inputs with all other product terms in the macroce

39、ll held low by one EPROM pull-down. Other patterns may result in longer delays than those specified. Delays involving only one product term, such as tPXZ, are specified for an “XOR-like” pattern which involves one pure input switching at a time, and the single product term. All tested parameters may

40、 not be tested on all macro cells. 5/ When the TURBO bit is not set, a non-TURBO adder of 30 ns maximum (40 ns for tASU) shall apply. Parameters may not be tested in non-TURBO condition, but shall be guaranteed to the limits specified in table I. Non-TURBO mode devices require one input or I/O trans

41、ition to guarantee entering correct power-up state. 6/ fMAXrepresents the highest clock frequency for pipelined data. 7/ May not be tested, but shall be guaranteed to the limits of tSUspecified in table I. 8/ May not be tested, but shall be guaranteed to the limits of tSUand tCO1specified in table I

42、. 9/ May not be tested, but shall be guaranteed to the limits of tCNTand tACNTspecified in table I. 10/ Same as tCNT. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89469 DLA LAND AND MARITIME COLUMBUS, OHIO

43、 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 Device type All Device type All Case outline X Case outline X Terminal number 1/ Terminal symbol Terminal number 1/ Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 GND I/O I/O I/O

44、I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I CLK1/I VCCCLK2/I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I CLK3/I VCC CLK4/I I I I I/O

45、 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 1/ Terminal numbers are referenced to the electrical pin one. FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89469 DLA LAND AND MA

46、RITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 Case outline Y 1 2 3 4 5 6 7 8 9 10 11 I/O I/O I CLK1/I CLK2/I I I/O I/O I/O L I/O I/O I/O I I VCCI I/O I/O I/O I/O K I/O I/O I/O I/O J I/O I/O I/O I/O H I/O I/O I/O I/O G I/O I/O I/O I/O F I/O I/O I/O I/O E I/O I/O I/O

47、I/O D I/O I/O 1/ I/O I/O C I/O I/O I/O I I VCCI I I/O I/O I/O B I/O I/O I/O I/O CLK4/I CLK3/I I I/O I/O A 1 2 3 4 5 6 7 8 9 10 11 BOTTOM VIEW 1/ Reference mark FIGURE 1. Terminal connections Continued. Truth table Input pins Output pins CP/I I I/O X X Z NOTES: 1. X = Dont care. 2. Z = High impedance. FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr