DLA SMD-5962-89501 REV E-2013 MICROCIRCUIT DIGITAL CMOS BUS CONTROLLER REMOTE TERMINAL MULTI-PROTOCOL MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R042-92. 91-11-25 Monica L. Poelking B Changes in accordance with NOR 5962-R080-93. 93-02-12 Monica L. Poelking C Correct delay time symbols in table I and figure 4. Update boilerplate to the requirements of MI

2、L-PRF-38535. Editorial changes throughout. TVN 01-05-02 Thomas M. Hess D Update boilerplate to current MIL-PRF-38535 requirements. CFS 07-06-11 Thomas M. Hess E Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 13-09-24 Thomas M. Hess REV SHEET REV E E E E E E E E E E E

3、E E E E E SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 REV STATUS REV E E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Todd D. Creek DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWI

4、NG THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Todd D. Creek APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, CMOS, BUS CONTROLLER REMOTE TERMINAL MULTI-PROTOCOL, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-08-16 REVISION LEVEL

5、 E SIZE A CAGE CODE 67268 5962-89501 SHEET 1 OF 30 DSCC FORM 2233 APR 97 5962-E577-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89501 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHE

6、ET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-895

7、01 01 X A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 UT1553 BCRTMP Bus controller remote terminal multi-protocol 1.2.2 Case o

8、utline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA7-P145 145 Pin grid array Y See figure 1 132 Unformed lead chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A

9、. 1.3 Absolute maximum ratings. 1/ Supply voltage range . -0.3 V to +7.0 V Dc input/dc output voltage range (VIN) . -0.3 V to (VDD+ 0.3 V) Maximum power dissipation (PD) . 300 mW 2/ Storage temperature range -65C to +150C Thermal resistance, junction-to-case (JC): Case X See MIL-STD-1835 Case Y 12C/

10、W Maximum junction temperature (TJ) . +175C Latchup immunity (ILU) 150 mA 1.4 Recommended operating conditions. Supply voltage range (VDD) 4.5 V to 5.5 V DC input voltage. 0 V to VDDCase operating temperature range (TC) . -55C to +125C _ 1/ Stresses above the absolute maximum rating may cause perman

11、ent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Must withstand the added PDdue to short circuit test (e.g., IOS). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRC

12、UIT DRAWING SIZE A 5962-89501 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent

13、 specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method S

14、tandard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.

15、mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094). 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this documen

16、t, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built

17、 to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifyin

18、g activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as describe

19、d herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3

20、.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 and figure 1 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 3. 3.2.4 Test circuit and

21、switching waveforms. The test circuit and switching waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperat

22、ure range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICR

23、OCIRCUIT DRAWING SIZE A 5962-89501 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN

24、 may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices buil

25、t in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manuf

26、acturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, a

27、ppendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA sha

28、ll be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made ava

29、ilable onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89501 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Elec

30、trical performance characteristics. Test Symbol Test conditions +4.5 V VDD +5.5 V -55C TC +125C unless otherwise specified Device type Group A subgroups Limits Unit Min Max Low level input voltage, TTL inputs VILAll 1, 2, 3 0.8 V High level input voltage, TTL inputs VIHAll 1, 2, 3 2.0 V Input leakag

31、e current, TTL inputs IIN1VIN= VDDor VSS All 1, 2, 3 -1 1 A Inputs with pull up resistors IIN2VIN = VDD All 1, 2, 3 -1 1 A VIN= VSS -550 -80 Low level output voltage, TTL outputs VOLIOL= 3.2 mA All 1, 2, 3 0.4 V High level output voltage, TTL outputs VOHIOH= -400 A All 1, 2, 3 2.4 V Three-state outp

32、ut leakage current, TTL outputs IOZVOH= VDDor VSS All 1, 2, 3 10 A Short circuit output current 1/ 2/ IOSVDD= 5.5 V, VO= VDD All 1, 2, 3 100 mA VDD= 5.5 V, VO= 0 V-100 Average operating current 1/ IDDF = 12 MHz, CL= 50 pF 4/ All 1, 2, 3 50 3/ mA Quiescent current 4/ QIDD All 1, 2, 3 3 mA Input capac

33、itance CINSee 4.3.1c All 4 10 pF Output capacitance COUT15 Bidirectional capacitance CIO20 Functional test See 4.3.1d All 7, 8 Burst DMA timing DMACK (L) to DMAR high impedance 1/ tSHL1See figure 4 All 9, 10, 11 0 10 ns DMAG (L) to DMACK (L) 5/ tPZL2All 9, 10, 11 0 45 ns DMAG (L) to TSCTL (L) 1/ tPH

34、L2All 9, 10, 11 2xMCLK 6/ 4xMCLK 6/ ns TSCTL (L) to address valid 1/ tPZL1 All 9, 10, 11 0 40 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89501 DLA LAND AND MARITIME COLU

35、MBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions +4.5 V VDD +5.5 V -55C TC +125C unless otherwise specified Device type Group A subgroups Limits Unit Min Max Burst DMA timing Continued RWR /

36、RRD (H) to DMACK (H) 1/ tHLH2 See figure 4 All 9, 10, 11 THMC1-10 7/ THMC1+10 7/ ns TSCTL (L) to RWR / RRD (L) tPHL3 All 9, 10, 11 MCLK-20 6/ MCLK+20 6/ ns DMAG (L) to DMAG (H) 1/ tPW2 All 9, 10, 11 MCLK 6/ 6xMCLK 6/ ns DMAR (L) to BURST(H) 8/ tOOZL1 All 9, 10, 11 -10 10 ns DMAR (L) to DMAG (L) 1/ t

37、PHL4 All 9, 10, 11 0 9/ 0 10/ 3.5 (1.9) 1.9 (0.8) s DMA read timing Address valid to RRD (L) (address setup) tSHL1 See figure 4 All 9, 10, 11 THMC2-10 11/ THMC2+5 11/ ns RRD (L) to RRD (H) tPW1 All 9, 10, 11 MCLK-10 6/ MCLK+5 6/ ns RRD (H) to address high impedance 1/ (address hold) tHLZ2 All 9, 10,

38、 11 THMC1-10 7/ THMC1+10 7/ ns RRD (H) to data high Impedance (data hold) tHLZ1 All 9, 10, 11 5 ns Data valid to RRD (H) (data setup) tSLH1 All 9, 10, 11 40 ns MCLK(H) to MCLKD2(H) tPLH1 All 9, 10, 11 0 40 ns MCLK(H) to TSCTL / MEMCSO (L) tPLH2 All 9, 10, 11 0 40 ns MCLK(H) to RRD (L) tIOHL1 All 9,

39、10, 11 0 60 ns DMA write timing Address valid to RWR (L) (address setup) tSHL1 See figure 4 All 9, 10, 11 THMC2-10 11/ THMC2+5 11/ ns RWR (L) to data valid 12/ tOOZL1 All 9, 10, 11 0 30 ns RWR (H) to data high impedance 1/ (data hold) tHLZ1 All 9, 10, 11 THMC1-10 7/ THMC1+10 7/ ns See footnotes at e

40、nd of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89501 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristic

41、s - Continued. Test Symbol Test conditions +4.5 V VDD +5.5 V -55C TC +125C unless otherwise specified Device type Group A subgroups Limits Unit Min Max DMA write timing Continued RWR (H) to address high impedance 1/ (address hold) tHLZ2 See figure 4 All 9, 10, 11 THMC1-10 7/ THMC1+10 7/ ns RWR (L) t

42、o RWR (H) tPW1 All 9, 10, 11 MCLK-10 6/ MCLK+5 6/ ns MCLK(H) to MCLKD2(H) tPLH1 All 9, 10, 11 0 40 ns MCLK(H) to TSCTL / MEMCSO (L) tPLH2 All 9, 10, 11 0 40 ns MCLK(H) to RWR (L) tIOHL1 All 9, 10, 11 0 60 ns Register read timing Address valid to data valid 13/ tOOZH2 See figure 4 All 9, 10, 11 80 ns

43、 RD + CS (H) to data high impedance 1/ (data hold) tHLH2 All 9, 10, 11 5 50 ns RD + CS (L) to data valid (data access) 13/ tOOZH1 All 9, 10, 11 60 ns RD + CS (H) to address invalid 1/ (address hold) tHLH1 All 9, 10, 11 5 ns RD + CS (L) to RD + CS (H) 1/ tPW1 All 9, 10, 11 60 ns RD + CS (H) to RD + C

44、S (L) 1/ tPW2 All 9, 10, 11 80 ns Register write timing Address valid to WR + CS (L) (address setup) tSHL1 See figure 4 All 9, 10, 11 60 ns Data valid WR + CS (L) (data setup) 1/ 14/ tSHL2 All 9, 10, 11 5 ns WR + CS (L) to WR + CS (H) tPW1 All 9, 10, 11 60 ns See footnotes at end of table. Provided

45、by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89501 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Sy

46、mbol Test conditions +4.5 V VDD +5.5 V -55C TC +125C unless otherwise specified Device type Group A subgroups Limits Unit Min Max Register write timing - Continued WR + CS (H) to data invalid (data hold) tHLH1 See figure 4 All 9, 10, 11 10 ns WR + CS (H) to address invalid (address hold) tHLH2 All 9

47、, 10, 11 10 ns WR + CS (H) to WR + CS (L) 1/ tPW2 All 9, 10, 11 80 ns Dual port interface timing RD (L) to RRD (L) tPHL1 See figure 4 All 9, 10, 11 0 30 ns WR (L) to RWR (L) tPHL2 All 9, 10, 11 0 30 ns MEMCSI (L) to MEMCSO (L) tPHL3 All 9, 10, 11 0 30 ns Memory window timing MEMWIN (H) to DMA activi

48、ty 1/ 15/ 16/ tOOLH1 See figure 4 All 9, 10, 11 9 s MEMWIN (L) to MEMWIN (H) 1/ tPW1 All 9, 10, 11 0 17/ s Data word to DMA activity 1/ 15/ 16/ tPZL1 All 9, 10, 11 0 4 s Arbitration when DMAG is asserted before arbitration timing DMAG (L) to DMAGO (L) 18/ tPHL1 See figure 4 All 9, 10, 11 0 30 ns DMACK (L) to DMAR high impedance 1/ tSHL1 All 9, 10, 11 0 10 ns MCLK(H) to MCLKD2(H) tPLH2 All 9, 10, 11 0 40 ns Legalization bus timing LGLEN (L) to LGLEN (H) tPW1 See figure 4 All 9, 10, 11 750 ns LGLEN (L) to legalization bus valid 1/ tHLH1 All 9,