DLA SMD-5962-89524 REV B-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 64K X 4 SRAM WITH OE MONOLITHIC SILICON《硅单片64K X 4静态存取存储器OE 互补型金属氧化物半导体数字存储微电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update document boilerplate. Add column for data retention to section 1.2.1. Convert case outline X reference to MIL-STD-1835. Add device types 06 and 07. Add CAGE codes 65786 and 0EU86 as sources of supply for device types 06 and 07. Editorial c

2、hanges throughout. 94-03-24 M. A. Frye B Boilerplate update, part of 5 year review. REDRAWN ksr 06-02-15 Raymond Monnin REV SHET REV B B B SHEET 15 16 17 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTE

3、R COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Monica L. Poelking COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-12-01 MICROCIRCUIT, MEMORY, DIGI

4、TAL, CMOS 64K X 4 SRAM WITH OE, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89524 SHEET 1 OF 17 DSCC FORM 2233 APR 97 5962-E224-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-

5、89524 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identi

6、fying Number (PIN). The complete PIN is as shown in the following example: 5962-89524 01 X A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit func

7、tion Data retention Access time 01 (See 6.6) 64K X 4 CMOS static RAM Yes 70 ns 02 (See 6.6) 64K X 4 CMOS static RAM Yes 55 ns 03 (See 6.6) 64K X 4 CMOS static RAM Yes 45 ns 04 (See 6.6) 64K X 4 CMOS static RAM Yes 35 ns 05 (See 6.6) 64K X 4 CMOS static RAM Yes 25 ns 06 (See 6.6) 64K X 4 CMOS static

8、RAM No 20 ns 07 (See 6.6) 64K X 4 CMOS static RAM No 15 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP4-T28 or CDIP3-T28 28 Dual-in-line package Y CQCC3-N28 28 rectangular leadless c

9、hip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Terminal voltage with respect to ground -0.5 V dc to +7.0 V dc DC output current 50 mA Storage temperature range . -65C to +150C Maximum power dissipation (PD) 1.0 W Lead temper

10、ature (soldering, 10 seconds). +260C Thermal resistance, junction-to-case (JC): Cases X, Y See MIL-STD-1835 Junction temperature (TJ). +150C 1/ 1.4 Recommended operating conditions. Supply voltage range (VCC) 4.5 V dc to 5.5 V dc High level input voltage range (VIH) 2.2 V dc to 6.0 V dc Low level in

11、put voltage range (VIL) -0.5 V dc to +0.8 V dc 2/ Case operating temperature range (TC) -55C to +125C 1/ Maximum junction temperature may be increased to +175C during burn-in and steady state life. 2/ VIL(min) = -3.0 V dc for pulse width less than 20 ns. Provided by IHSNot for ResaleNo reproduction

12、or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89524 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following s

13、pecification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, Genera

14、l Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Dra

15、wings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between th

16、e text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shal

17、l be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification

18、 to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These mod

19、ifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dime

20、nsions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Truth table. The truth table shall be as specified on figure 2. 3.2.3 Case outlines.

21、The case outlines shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requir

22、ements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition,

23、 the manufacturers PIN may also be marked. For packages where the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN d

24、evices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without l

25、icense from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89524 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions Group A Device Limits Unit -55C TC +125C subgroups types

26、 VCC= 4.5 V to 5.5 V Min Max unless otherwise specified Output high voltage VOHVCC= 4.5 V, IOH= -4.0 mA, 1,2,3 All 2.4 V VIL= 0.8 V, VIH= 2.2 V Output low voltage VOLVCC= 4.5 V, IOL= 8.0 mA 1,2,3 All 0.4 V VIL= 0.8 V, VIH= 2.2 V Input leakage current ILIVCC= 5.5 V, GND VCC- 0.2 V 1,2,3 01-05 1 mA su

27、pply current 1/ f = 0 MHz, Applies only to devices with data retention. Input capacitance CINVCC= 5.0 V, VIN= 0 V, 4 All 11 pF f = 1.0 MHz, TA= +25C, see 4.3.1c Output capacitance COUTVCC= 5.0 V, VOUT= 0 V, 4 All 11 pF f = 1.0 MHz, TA= +25C see 4.3.1c Functional tests See 4.3.1d 7, 8A, 8B All See fo

28、otnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89524 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical perfo

29、rmance characteristics - Continued. Test Symbol Conditions Group A Device Limits Unit -55C TC +125C subgroups types VCC= 4.5 V to 5.5 V Min Max unless otherwise specified Read cycle time tAVAVSee figures 3 and 4 2/ 9,10,11 01 70 ns 02 55 03 45 04 35 05 25 06 20 07 15 Address access time tAVQV 9,10,1

30、1 01 70 ns 02 55 03 45 04 35 05 25 06 20 07 15 Output hold from tAVQX 9,10,11 All 3.0 ns address change Chip select access time tELQV 9,10,11 01 70 ns 02 55 03 45 04 35 05 25 06 20 07 15 Chip select to output tELQXSee figures 3 and 4 3/ 4/ 9,10,11 All 3.0 ns in low Z See footnotes at end of table. P

31、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89524 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - C

32、ontinued. Test Symbol Conditions Group A Device Limits Unit -55C TC +125C subgroups types VCC= 4.5 V to 5.5 V Min Max unless otherwise specified Chip deselect to output tEHQZSee figures 3 and 4 3/ 4/ 9,10,11 01 30 ns in high Z 02 25 03 20 04,05 15 06 10 07 8 Output enable to output tOLQVSee figures

33、3 and 4 9,10,11 01 45 ns valid 02 35 03 30 04 25 05 15 06 10 07 8 Output enable to output tOLQXSee figures 3 and 4 3/ 4/ 9,10,11 All 0 ns in low Z Output disable to output tOHQZ 9,10,11 01 25 ns in high Z 02-04 20 05 15 06,07 9 Write cycle time tAVAVSee figures 3 and 5 2/ 9,10,11 01 70 ns 02 55 03 4

34、5 04 35 05 25 06 20 07 15 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89524 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234

35、APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions Group A Device Limits Unit -55C TC +125C subgroups types VCC= 4.5 V to 5.5 V Min Max unless otherwise specified Chip select to end of tELEHSee figures 3 and 5 2/ 9,10,11 01-03 30 ns write 04 25 05 20 06 15 07

36、10 Address valid to end of tAVWH 9,10,11 01-03 30 ns write 04 25 05 20 06 15 07 10 Address setup time tAVWL 9,10,11 All 0 ns Write pulse width tWLWH 9,10,11 01-03 30 ns 04 25 05 20 06 15 07 10 Write recovery time tWHAX 9,10,11 All 0 ns tEHAX Data valid to end of tDVWH 9,10,11 01-04 20 ns write 05 15

37、 06 10 07 9 Data hold time tWHDX 9,10,11 All 0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89524 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B

38、 SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions Group A Device Limits Unit -55C VCC-0.2 V, 9,10,11 All 0 ns retention time see figure 6 3/ Operation recovery time tR 9,10,11 All tAVAV ns 1/ At f = fMAXaddress and data inputs are cycl

39、ing at the maximum frequency of read cycles of 1/tAVAV. f = 0 means no input lines change. 2/ Test conditions assume signal transition times of 5.0 ns or less. Timing is referenced at input and output levels of 1.5 V and input pulse levels of 0 to 3.0 V. Output loading is equivalent to the specified IOL/IOHwith a load capacitance of 30 pF. 3/ If not tested, shall be guaranteed to the limits specified in table I. 4/ Test