DLA SMD-5962-89575 REV D-2013 MICROCIRCUIT DIGITAL CMOS REMOTE TERMINAL FOR STORES WITH 1K X 16 RAM MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R114-95. - LTG 95-04-13 Monica L. Poelking B Update boilerplate to the requirements of MIL-PRF-38535. Editorial changes throughout. TVN 01-05-25 Thomas M. Hess C Update boilerplate to current MIL-PRF-38535 requ

2、irements. CFS 07-06-12 Thomas M. Hess D Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 13-09-24 Thomas M. Hess REV SHEET REV D D D D D D D D D SHEET 15 16 17 18 19 20 21 22 23 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14

3、PMIC N/A PREPARED BY Christopher A. Rauch DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Tim H. Noh APPROVED BY William

4、K. Heckman MICROCIRCUIT, DIGITAL, CMOS, REMOTE TERMINAL FOR STORES WITH 1K X 16 RAM, MONOLITHIC SILICON DRAWING APPROVAL DATE 90-04-27 REVISION LEVEL D SIZE A CAGE CODE 67268 5962-89575 SHEET 1 OF 23 DSCC FORM 2233 APR 97 5962-E576-13 Provided by IHSNot for ResaleNo reproduction or networking permit

5、ted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89575 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuit

6、s in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89575 01 X A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the

7、 circuit function as follows: Device type Generic number Circuit function 01 UT1760A RTS Remote terminal for stores with 1K x 16 RAM 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA15-P68

8、 68 Pin grid array Y CQCC2-J68 68 Unformed-lead chip carrier Z CQCC1-N68 68 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VDD) -0.3 V dc minimum to +7.0 V dc maximum DC input/dc out

9、put voltage range (VIN) . -0.3 V dc minimum to 7.3 V dc maximum Maximum power dissipation (PD) . 300 mW 2/ Storage temperature range -65C to +150C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Lead temperature (soldering, 10 seconds) . +300C Maximum junction temperature (TJ) . +175C L

10、atchup immunity (ILU) 150 mA 1.4 Recommended operating conditions. Supply voltage range (VDD) 4.5 V dc minimum to 5.5 V dc maximum Minimum high level input voltage (VIH) . 5.5 V dc Maximum low level input voltage (VIL) 0.0 V dc Case operating temperature range (TC) . -55C to +125C Operating frequenc

11、y (FO) . 12 MHz VSS. 0.0 V dc _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Must withstand the added PDdue to short circuit test (e.g., IOS). Provided by IHSNot for

12、 ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89575 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. T

13、he following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufac

14、turing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Mi

15、crocircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094). 2.2 Order of precedence. In the event of a conflict between the text of this drawing and t

16、he references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-

17、PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be pro

18、cessed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect

19、form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construc

20、tion, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Functional block diagram. The fu

21、nctional block diagram shall be as specified on figure 2. 3.2.4 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics

22、are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleN

23、o reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89575 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shal

24、l be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compli

25、ance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Cert

26、ificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall

27、 affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.

28、8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facilit

29、y and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89575 DLA LAND AND MARITIME COLUM

30、BUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions +4.5 V VDD +5.5 V -55C TC +125C unless otherwise specified Device type Group A subgroups Limits Unit Min Max Low level input voltage, TTL inputs VILAll 1,

31、2, 3 0.8 V High level input voltage VIH All 1, 2, 3 2.0 V Input leakage current, TTL inputs IIN1VIN= VDDor VSS All 1, 2, 3 -1 1 A Inputs with pull-down resistors IIN2VIN= VDD 110 2000 Inputs with pull-up resistors IIN3 VIN = VSS -2000 -110 Low level output voltage VOL IOL = 3.2 mA All 1, 2, 3 0.4 V

32、High level output voltage VOH IOH= -400 A All 1, 2, 3 2.4 V Three-state output leakage current, TTL outputs IOZVO = VDD or VSS All 1, 2, 3 -10 10 A Short circuit output current 1/ 2/ IOSVDD= 5.5 V, VO= VDD All 1, 2, 3 90 mA VDD= 5.5 V, VO= 0 V-90 Quiescent current 3/ QIDD All 1, 2, 3 1.5 mA Average

33、operating current 1/ 4/ IDDF = 12 MHz, CL= 50 pF All 1, 2, 3 50 mA Input capacitance CINSee 4.3.1c All 4 10 pF Output capacitance COUT15 Bidirectional I/O capacitance CIO20 Functional test See 4.3.1d All 7, 8 Microprocessor RAM read cycle CTRL (H) setup wrt CS (L) 5/ t1See figure 3 1/ All 9, 10, 11

34、10 ns RD/ WR (H) setup wrt CS (L) 5/ t2All 9, 10, 11 10 ns ADDR (9:0) valid to CS (L) (address setup) t3All 9, 10, 11 10 ns CS (L) to DATA (15:0) valid t4 All 9, 10, 11 155 ns OE (L) to DATA (15:0) dont care (active) t5 All 9, 10, 11 65 ns See footnotes at end of table. Provided by IHSNot for Resale

35、No reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89575 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions

36、 +4.5 V VDD +5.5 V -55C TC +125C unless otherwise specified Device type Group A subgroups Limits Unit Min Max Microprocessor RAM read cycle Continued CS (H) to CTRL dont care t6 See figure 3 1/ All 9, 10, 11 0 ns CS (H) to ADDR (9:0) dont care t7 All 9, 10, 11 0 ns OE (H) to DATA (15:0) high impedan

37、ce t8 All 9, 10, 11 40 ns CS (L) to CS (H) 6/ t9 All 9, 10, 11 220 5500 ns CS (H) to CS (L) t10 All 9, 10, 11 85 ns CS (H) to RD/ WR dont care t11 All 9, 10, 11 0 ns CS (H) to DATA (15:0) invalid 7/ t12 All 9, 10, 11 25 ns OE (L) to OE (H) t13 All 9, 10, 11 65 ns Microprocessor RAM write cycle CTRL

38、(H) setup wrt CS (L) 5/ t1 See figure 3 1/ All 9, 10, 11 10 ns RD/ WR (L) setup wrt CS (L) 5/ t14All 9, 10, 11 10 ns ADDR (9:0) valid to CS (L) (address setup) t3All 9, 10, 11 10 ns DATA (15:0) valid to CS (L) (data setup) t15All 9, 10, 11 0 ns OE (H) to DATA (15:0) high impedance t16 All 9, 10, 11

39、40 ns CS (H) to RD/ WR dont care t11 All 9, 10, 11 0 ns CS (H) to ADDR (9:0) dont care t7 All 9, 10, 11 0 ns CS (H) to DATA (15:0) dont care (hold time) t17 All 9, 10, 11 20 ns CS (L) to CS (H) 6/ t18 All 9, 10, 11 180 5500 ns CS (H) to CS (L) t10 All 9, 10, 11 85 ns CS (H) to CTRL dont care t6 All

40、9, 10, 11 0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89575 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Elec

41、trical performance characteristics - Continued. Test Symbol Test conditions +4.5 V VDD +5.5 V -55C TC +125C unless otherwise specified Device type Group A subgroups Limits Unit Min Max Control register write cycle CTRL (L) setup wrt CS (L) 5/ t19 See figure 3 1/ All 9, 10, 11 0 ns RD/ WR (L) setup w

42、rt CS (L) 5/ t20All 9, 10, 11 0 ns CS (L) to CS (H) 6/ t21 All 9, 10, 11 50 5500 ns CS (H) to DATA (15:0) dont care (hold time) t22 All 9, 10, 11 0 ns CS (H) to CTRL dont care t6 All 9, 10, 11 0 ns CS (H) to RD/ WR dont care t11 All 9, 10, 11 0 ns OE (H) to DATA (15:0) high impedance t23 All 9, 10,

43、11 40 ns DATA (15:0) valid to CS (L) (data setup) t15All 9, 10, 11 0 ns Status register read cycle CTRL (L) setup wrt CS (L) 5/ t19 See figure 3 1/ All 9, 10, 11 0 ns CS (L) to CS (H) 6/ t24 All 9, 10, 11 65 5500 ns RD/ WR (H) setup wrt CS (L) 5/ t25All 9, 10, 11 0 ns CS (L) to DATA (15:0) valid t26

44、 All 9, 10, 11 65 ns CS (H) to CTRL dont care t27 All 9, 10, 11 5 ns CS (H) to RD/ WR dont care t28 All 9, 10, 11 5 ns OE (L) to DATA (15:0) dont care (active) t5 All 9, 10, 11 65 ns OE (H) to DATA (15:0) high impedance t8 All 9, 10, 11 40 ns OE (L) to OE (H) t13 All 9, 10, 11 65 ns CS (L) to DATA (

45、15:0) dont care (active) t29 All 9, 10, 11 25 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89575 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 D

46、SCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions +4.5 V VDD +5.5 V -55C TC +125C unless otherwise specified Device type Group A subgroups Limits Unit Min Max RT fail safe timer signal relationships VALMSG (H) before TIMERON (L) t30 See fig

47、ure 3 1/ All 9, 10, 11 0 35 ns TIMERON (L) before first biphase out zero (H) t31 All 9, 10, 11 1.2 s TIMERON low pulse width (time-out) t32 All 9, 10, 11 727.3 727.4 s COMSTR (L) to TIMERON (H) t33 All 9, 10, 11 25 ns VALMSG (H) to ILLCOM (H) 8/ t34 All 9, 10, 11 3.3 s COMSTR (L) to ILLCOM (H) 9/ t3

48、5 All 9, 10, 11 664 ns COMSTR (L) to ILLCOM (H) 9/ t35 All 9, 10, 11 18.2 s ILLCOM (H) to ILLCOM (L) 10/ t36 All 9, 10, 11 500 ns Status output timing 12 MHz (H) to MC /SA valid t37 See figure 3 All 9, 10, 11 0 180 ns Command word to MC /SA valid 1/ 11/ t38 All 9, 10, 11 2.1 2.8 s 12 MHz (H) to COMSTR (L) t39 All 9, 10, 11 0 100 ns Command word to COMSTR (L) 1/ 11/ t40 All 9, 10, 11 3.2 3.7 s 12 MHz (H) to BRDCST (L) t41 All 9, 10, 11 0 115 ns Command word to BRDCST (L) 1/ 11/ t42 All 9, 10, 11 2.6 3