DLA SMD-5962-89603 REV B-2011 MICROCIRCUIT DIGITAL HIGH SPEED CMOS 8-INPUT BINARY COUNTER WITH THREE-STATE OUTPUT REGISTERS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add notes and correct waveforms in figure 4, switching waveforms and test circuit. Update the boilerplate to current requirements as specified in MIL-PRF-38535. Editorial changes throughout. jak. 05-08-31 Thomas M. Hess B Update the boilerplate p

2、aragraphs to current requirements as specified in MIL-PRF-38535. - MAA. 11-10-19 Thomas M. Hess REV SHEET REV B SHEET 15 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Monica L. Poelking DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990

3、 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, 8-INPUT BINARY COUNTER WITH THREE-STATE OUTPUT REGISTERS, MONOLITHIC SILICON AND AGENCIES OF

4、 THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-07-07 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89603 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E505-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE

5、A 5962-89603 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identify

6、ing Number (PIN). The complete PIN is as shown in the following example: 5962-89603 01 E A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit fun

7、ction 01 54HC590A 8-input binary counter with three-state output registers 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 F

8、lat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC + 0.5 V dc DC output voltage range (V

9、OUT) . -0.5 V dc to VCC+ 0.5 V dc Clamp diode current (IIK, IOK) . 20 mA DC output current (per pin) (IOUT) . 35 mA DC VCCor GND current (per pin) (ICC, IGND) . 70 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) 2/ 500 mW Lead temperature (soldering, 10 seconds) +3

10、00C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) +2.0 V dc to +6.0 V dc Input voltage range (VIN) +0.0 V dc to VCCOutput voltage range (VOUT). +0.0 V dc to VCCCase operating temperature r

11、ange (TC) . -55C to +125C Input rise or fall time (tr, tf): VCC= 2.0 V 0 to 1000 ns VCC= 4.5 V 0 to 500 ns VCC= 6.0 V 0 to 400 ns 1/ Unless other wise specified, all voltages are referenced to ground. 2/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction

12、 or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89603 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions Continued. Minimum setup time, CCKEN low before CCK rising (ts1):

13、TC= +25C: VCC= 2.0 V 100 ns VCC= 4.5 V 20 ns VCC= 6.0 V 17 ns TC= -55C to +25C: VCC= 2.0 V 150 ns VCC= 4.5 V 30 ns VCC= 6.0 V 26 ns Minimum setup time, CCLR high (inactive) before CCK rising (ts2): TC= +25C: VCC= 2.0 V 100 ns VCC= 4.5 V 20 ns VCC= 6.0 V 17 ns TC= -55C to +25C: VCC= 2.0 V 150 ns VCC=

14、 4.5 V 30 ns VCC= 6.0 V 26 ns Minimum setup time, CCK rising before RCK rising (ts3): 3/ TC= +25C: VCC= 2.0 V 100 ns VCC= 4.5 V 20 ns VCC= 6.0 V 17 ns TC= -55C to +25C: VCC= 2.0 V 150 ns VCC= 4.5 V 30 ns VCC= 6.0 V 26 ns Minimum hold time, CCKEN low after CCK rising (th): TC= +25C: VCC= 2.0 V 50 ns

15、VCC= 4.5 V 10 ns VCC= 6.0 V 9 ns TC= -55C to +25C: VCC= 2.0 V 75 ns VCC= 4.5 V 15 ns VCC= 6.0 V 13 ns Minimum pulse width, CCK or RCK high or low (tw1): TC= +25C: VCC= 2.0 V 125 ns VCC= 4.5 V 25 ns VCC= 6.0 V 21 ns TC= -55C to +25C: VCC= 2.0 V 200 ns VCC= 4.5 V 38 ns VCC= 6.0 V 32 ns Minimum pulse w

16、idth, CCLR low (tw2): TC= +25C: VCC= 2.0 V 100 ns VCC= 4.5 V 20 ns VCC= 6.0 V 17 ns TC= -55C to +25C: VCC= 2.0 V 150 ns VCC= 4.5 V 30 ns VCC= 6.0 V 26 ns 3/ This setup time ensures the register will see stable data from the counter outputs. The clocks may be tied together in which case the register

17、will be one clock pulse behind the counter. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89603 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE D

18、OCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF

19、DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 -

20、List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order

21、of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item

22、 requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufact

23、urer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make

24、 modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option

25、is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal conne

26、ctions shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figu

27、re 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89603 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless ot

28、herwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for e

29、ach subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasibl

30、e due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replace

31、d with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 here

32、in). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conf

33、ormance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Lan

34、d and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or

35、 networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89603 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C unless otherwise

36、specified VCCGroup A subgroups Limits Unit Min Max High level output voltage VOHVIN= VIHminimum or VILmaximum IOH= -20 A 2.0 V 1, 2, 3 1.9 V 4.5 V 4.4 6.0 V 5.9 VIN= VIHminimum or VILmaximum IOH= -6.0 mA for QA-QH IOH= -4.0 mA for RCO4.5 V 3.7 VIN= VIHminimum or VILmaximum IOH= -7.8 mA for QA-QH IOH

37、= -5.2 mA for RCO6.0 V 5.2 Low level output voltage VOLVIN= VIHminimum or VILmaximum IOL= 20 A 2.0 V 1, 2, 3 0.1 V 4.5 V 0.1 6.0 V 0.1 VIN= VIHminimum or VILmaximum IOL= 6.0 mA for QA-QH IOL= 4.0 mA for RCO4.5 V 0.4 VIN= VIHminimum or VILmaximum IOL= 7.8 mA for QA-QH IOL= 5.2 mA for RCO6.0 V 0.4 Hig

38、h level input voltage VIH2/ 2.0 V 1, 2, 3 1.5 V 4.5 V 3.15 6.0 V 4.2 Low level input voltage VIL2/ 2.0 V 1, 2, 3 0.3 V 4.5 V 0.9 6.0 V 1.2 Input capacitance CINTC= +25C VIN= 0 V See 4.3.1c 4 10 pF Quiescent supply current ICCVIN= VCCor GND 6.0 V 1, 2, 3 160 A Input leakage current IINVIN= VCCor GND

39、6.0 V 1, 2, 3 1 A Off-state output leakage current IOZVIN= VIHor VIL VOUT= VCCor GND IOUT= 0.0 A 6.0 V 1, 2, 3 10 A Functional tests See 4.3.1d 7, 8 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT

40、DRAWING SIZE A 5962-89603 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TC +125C unless otherwise specified VCCGroup A subgroups Limits Unit Min Max Propagation

41、delay time, CCK rising to RCOtPHL1, tPLH1 CL= 50 pF See figure 4 2.0 V 9 150 ns 4.5 V 31 6.0 V 26 2.0 V 10, 11 225 ns 4.5 V 45 6.0 V 38 Propagation delay time, CCLR falling to RCOtPLH2 CL= 50 pF See figure 4 2.0 V 9 130 ns 4.5 V 28 6.0 V 23 2.0 V 10, 11 195 ns 4.5 V 39 6.0 V 33 Propagation delay tim

42、e, RCK rising to Qn tPHL3, tPLH3 CL= 50 pF See figure 4 2.0 V 9 140 ns 4.5 V 31 6.0 V 25 2.0 V 10, 11 210 ns 4.5 V 42 6.0 V 36 Propagation delay time, output enable, Gfalling to Qn tPZH, tPZL CL= 50 pF See figure 4 2.0 V 9 125 ns 4.5 V 30 6.0 V 28 2.0 V 10, 11 185 ns 4.5 V 37 6.0 V 31 Propagation de

43、lay time, output disable, Grising to Qn tPHZ, tPLZ CL= 50 pF See figure 4 2.0 V 9 125 ns 4.5 V 30 6.0 V 28 2.0 V 10, 11 185 ns 4.5 V 37 6.0 V 31 Transition time, RCOtTLH1, tTHL13/ CL= 50 pF See figure 4 2.0 V 9 75 ns 4.5 V 15 6.0 V 13 2.0 V 10, 11 110 ns 4.5 V 22 6.0 V 19 See footnotes at end of tab

44、le. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89603 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continu

45、ed. Test Symbol Conditions 1/ -55C TC +125C unless otherwise specified VCCGroup A subgroups Limits Unit Min Max Transition time, Qn tTLH2, tTHL23/ CL= 50 pF See figure 4 2.0 V 9 60 ns 4.5 V 12 6.0 V 10 2.0 V 10, 11 90 ns 4.5 V 18 6.0 V 15 Maximum frequency, CCK or RCK fMAX CL= 50 pF See figure 4 2.0

46、 V 9 4.0 MHz 4.5 V 20 6.0 V 24 2.0 V 10, 11 2.5 MHz 4.5 V 13 6.0 V 16 1/ For power supply of 5 V 10 percent, the worst case output voltages (VOHand VOL) occur for high-speed CMOS at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst cases VIHand VILoccur at VCC= 5.5

47、V and 4.5 V, respectively. The VIHvalue at 5.5 V is 3.85 V. The worst case leakage currents (IIN, ICC, and IOZ) occur for high-speed CMOS at the higher voltages so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically 250 pF determines the no load dynamic power consumption,

48、 PD= CPD VCC2f + ICCVCC, and the no load dynamic current consumption, PD= CPDVCCf + ICC. 2/ VIHand VILtests are not required and shall be applied as forcing functions for VOHor VOLtests. 3/ Transition times (tTLH, tTHL), if not tested, shall be guaranteed to the specified limits in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89603 DLA LAND AND MA