ImageVerifierCode 换一换
格式:PDF , 页数:12 ,大小:109.75KB ,
资源ID:699538      下载积分:10000 积分
快捷下载
登录下载
邮箱/手机:
温馨提示:
如需开发票,请勿充值!快捷下载时,用户名和密码都是您填写的邮箱或者手机号,方便查询和重复下载(系统自动生成)。
如填写123,账号就是123,密码也是123。
特别说明:
请自助下载,系统不会自动发送文件的哦; 如果您已付费,想二次下载,请登录后访问:我的下载记录
支付方式: 支付宝扫码支付 微信扫码支付   
注意:如需开发票,请勿充值!
验证码:   换一换

加入VIP,免费下载
 

温馨提示:由于个人手机设置不同,如果发现不能下载,请复制以下地址【http://www.mydoc123.com/d-699538.html】到电脑端继续下载(重复下载不扣费)。

已注册用户请登录:
账号:
密码:
验证码:   换一换
  忘记密码?
三方登录: 微信登录  

下载须知

1: 本站所有资源如无特殊说明,都需要本地电脑安装OFFICE2007和PDF阅读器。
2: 试题试卷类文档,如果标题没有明确说明有答案则都视为没有答案,请知晓。
3: 文件的所有权益归上传用户所有。
4. 未经权益所有人同意不得将文件中的内容挪作商业或盈利用途。
5. 本站仅提供交流平台,并不能对任何下载内容负责。
6. 下载文件中如有侵权或不适当内容,请与我们联系,我们立即纠正。
7. 本站不保证下载资源的准确性、安全性和完整性, 同时也不承担用户因使用这些下载资源对自己和他人造成任何形式的伤害或损失。

版权提示 | 免责声明

本文(DLA SMD-5962-89657 REV C-2013 MICROCIRCUIT LINEAR DUAL CMOS 12-BIT D A CONVERTER MONOLITHIC SILICON.pdf)为本站会员(tireattitude366)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA SMD-5962-89657 REV C-2013 MICROCIRCUIT LINEAR DUAL CMOS 12-BIT D A CONVERTER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R120-92. 92-01-27 Michael A. Frye B Drawing updated to reflect current requirements. - lgt 01-12-17 Raymond Monnin C Redrawn. Update paragraphs to MIL-PRF-38535 requirements. - drw 13-09-20 Charles F. Saffle TH

2、E ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV SHEET REV STATUS REV C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Rick C. Officer DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAW

3、ING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Charles E. Besore APPROVED BY Michael A. Frye MICROCIRCUIT, LIINEAR, DUAL, CMOS, 12-BIT, D/A CONVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-12-28 AMSC N/A REVISION LEVEL C SIZE A CAG

4、E CODE 67268 5962-89657 SHEET 1 OF 11 DSCC FORM 2233 APR 97 5962-E575-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89657 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FOR

5、M 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89657 01 L A Dra

6、wing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function Gain error 01 7547S Dual, CMOS, 12-bit D/A converter 6.0 LSB 02 7547T Dual, CMOS, 12-bit D/A

7、 converter 3.0 LSB 03 7547U Dual, CMOS, 12-bit D/A converter 2.0 LSB 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 3 CQCC1-N28 28 Square leadless chip carrier

8、 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. VDDto DGND . 0.3 V dc to +17 V dc VREFA, VREFB, to AGND 25 V dc VRFBA, VRFBB, to AGND 25 V dc Digital input voltage to DGND . 0.3 V dc to VDD+0.3 V Voltage at IOUTA, IOUTBto DGND -0.3 V dc

9、 to VDD+0.3 V AGND to DGND -0.3 V dc to VDD+0.3 V Storage temperature range . -65C to +150C Lead temperature (soldering, 10 seconds) +300C Power dissipation (PD) 450 mW 1/ Thermal resistance, junction to case (JC). See MIL-STD-1835 Thermal resistance, junction to ambient (JA) . 120C C/W Junction tem

10、perature (TJ) +175C 1.4 Recommended operating conditions. Supply voltage range (VDD) . 10.8 V dc to 16.5 V dc Minimum high level input voltage 2.4 V dc Maximum low level input voltage . 0.8 V dc Ambient operating temperature range (TA) . -55C to +125C Voltage at VREFA, VREFB. 10 V dc Voltage at AGND

11、, IOUTA. 0 V dc Voltage at AGND, IOUTB. 0 V dc _ 1/ Derate above TA= +75C at 6.0 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89657 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SH

12、EET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in t

13、he solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPA

14、RTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphi

15、a, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtai

16、ned. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualifi

17、ed manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality

18、Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to ident

19、ify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal co

20、nnections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall

21、 apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permi

22、tted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89657 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA+125C unless otherwise specified Group A

23、subgroups Device type Limits Unit Min Max Resolution 2/ RES Guaranteed minimum resolution 1, 2, 3 All 12 Bits Relative accuracy RA VDD = 10.8 V and 16.5 V 1, 2, 3 01 1.0 LSB 1 02, 03 1.0 2, 3, 12 0.5 Differential nonlinearity DNL Guaranteed monotonic to 12-bits , VDD= 10.8 V and 16.5 V 1, 2, 3 All 1

24、.0 LSB Gain error AE Measured using RFBA and RFBB. Both DAC registers loaded with all 1s, VDD= 10.8 V. 1, 2, 3 01 6.0 LSB 1 02 3.0 03 2.0 2, 3, 12 02 3.0 03 2.0 Gain temperature 2/ coefficient TAE4 All 5.0 ppm/C Power supply rejection ratio, VREFBto IOUTBPSRR VDD = 10.8 V and 16.5 V 1 All 0.01 %/% V

25、DD = 10.8 V 2, 3 0.02 Output leakage current IOUTA DAC A loaded with all 0s, VDD= 16.5 V 1 All 10 nA 2, 3 250 IOUTB DAC B loaded with all 0s, VDD= 16.5 V 1 All 10 nA 2, 3 250 Output current settling 2/ time to 0.01% of FSR tSLIOUTload = 100, CEXT= 13 pF, DAC output measured from falling edge of WR 9

26、 All 1.5 s 10, 11 1.5 Feedthrough error, 2/ VREFAto IOUTAor VREFBto IOUTBFT VREFA= VREFB= 20 Vpp, 10 kHz sine wave, DAC register loaded with all 0s 4 All -65 dB 5, 6 -65 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-S

27、TANDARD MICROCIRCUIT DRAWING SIZE A 5962-89657 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions 1/ -55C TA+125C unless otherwise specified Group A subgroups Device type Lim

28、its Unit Min Max Reference input resistance RINVDD= 10.8 V 1, 2, 3 All 9.0 20 k Reference input resistance match (VREFA/VREFB) RMINVDD= 10.8 V 1, 2, 3 01, 02 3.0 % 1 03 3.0 2, 3 1.0 Digital input high voltage VIH VDD = 10.8 V and 16.5 V 1, 2, 3 All 2.4 V Digital input low voltage VIL VDD = 10.8 V an

29、d 16.5 V 1, 2, 3 All 0.8 V Input current IIN VIN = VDD = 16.5 V 1 All 1.0 A 2, 3 10 Digital input capacitance 2/ CINTA= +25C 4 All 10 pF Output capacitance 2/ COUTA DAC A = all 0s, TA= +25C 4 All 70 pF DAC A = all 1s, TA= +25C 140 Output capacitance 2/ COUTB DAC B = all 0s, TA= +25C 4 All 70 pf DAC

30、B = all 1s, TA= +25C 140 Functional test See 4.3.1c 7 All Data setup time tDS See figure 3 9 All 60 ns 10, 11 2/ 80 Data hold time tDH See figure 3 9 All 25 ns 10, 11 2/ 25 Chip select or update to write setup time tCWSSee figure 3 9 All 80 ns 10, 11 2/ 100 Chip select or update to write hold time t

31、CWHSee figure 3 9 All 0 ns 10, 11 2/ 0 Write pulse width tWR See figure 3 9 All 80 ns 10, 11 2/ 100 Supply current IDD VDD = 16.5 V 1, 2, 3 All 2.0 mA 1/ VDD= 10.8 V to 16.5 V, unless otherwise specified. VREFA= VREFB= 10 V, voltage at AGND = 0 V, voltage at IOUTA= IOUTB= 0 V. 2/ If not tested, shal

32、l be guaranteed to the limits specified in table I herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89657 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97

33、Device type 01, 02, 03 02 Case outline L 3 Terminal number Terminal symbol Terminal symbol 1 AGND NC 2 IOUTA AGND 3 RFBA IOUTA 4 VREFA RFBA 5 CSA VREFA6 DB0(LSB) CSA 7 DB1 DB0(LSB) 8 DB2 NC 9 DB3 DB1 10 DB4 DB2 11 DB5 DB3 12 DGND DB4 13 DB6 DB5 14 DB7 DGND 15 DB8 NC 16 DB9 DB6 17 DB10 DB7 18 DB11(MS

34、B) DB8 19 WR DB920 CSB DB1021 VDD DB11(MSB) 22 VREFB NC 23 RFBB WR 24 IOUTB CSB 25 - VDD 26 - VREFB 27 - RFBB 28 - IOUTB FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89657 D

35、LA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 CSA CSB WR Function X X 1 No data transfer 1 1 X No data transfer 0 A rising edge on CSA or CSB loads data to the respective DAC from data bus 0 1 DACA register loaded from data bus 1 0 DACB register loaded

36、 from data bus 0 0 DACA and DACB register loaded from data bus 0 = Logic low level 1 = Logic high level X = Irrelevant = Rising edge triggered FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A

37、 5962-89657 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 Notes 1. All input signal rise and fall times are measured from 10% to 90% of +5.0 V, tr = tf = 20 ns. 2. Timing measurement reference level is 2V V ILIH +FIGURE 3. Timing diagram. Provided by

38、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89657 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendi

39、x A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Ce

40、rtification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option

41、 is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved sour

42、ce of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered t

43、o this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the man

44、ufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Scree

45、ning shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintain

46、ed by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MI

47、L-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. c. Subgroup 12 test is used for grading and part selection at +2

48、5C and is not included in PDA calculations. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89657 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 10 DSCC FORM 2234 APR 97 TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accord

copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
备案/许可证编号:苏ICP备17064731号-1