DLA SMD-5962-89661 REV A-2011 MICROCIRCUIT MEMORY DIGITAL CMOS CASCADABLE 64 X 9 FIFO MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated boilerplate as part of 5-year review. - glg 11-01-28 Charles Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV A A SHEET 15 16 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10

2、11 12 13 14 PMIC N/A PREPARED BY Steve L. Duncan DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY William K. Heckman MICROCIRCUIT, MEMORY, DIGITAL, CMOS, CA

3、SCADABLE 64 X 9 FIFO, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 22 AUGUST 1989 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-89661 SHEET 1 OF 16 DSCC FORM 2233 APR 97 5962-E186-11 .Provided by IHSNot for ResaleNo reproduction or networking permitted w

4、ithout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89661 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in

5、accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89661 01 X X Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circ

6、uit function as follows: Device type Generic number Circuit function Shift Rate 01 7C409A 64 X 9 FIFO 15 MHz 02 7C409A 64 X 9 FIFO 25 MHz 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See f

7、igure 1 28 Dual-in-line package Y GDFP2-F28 28 Flat package 3 CQCC1-N28 28 Square chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range -0.5 V dc to +7.0 V dc DC input voltage -3.0 V dc to +7.0 V dc DC

8、 output current . 20 mA Maximum power dissipation . 1.0 W Lead temperature (soldering, 10 seconds) . +260C Thermal resistance, junction to case: Cases Y and 3 . See MIL-STD-1835 Case X . 26C/W 1/ Junction temperature (TJ) . +150C 2/ Storage temperature range . -65C to +150C Temperature under bias .

9、-55C to +125C 1.4 Recommended operating conditions. Supply voltage range(VCC) . +4.5 V dc to +5.5 V dc Ground voltage (GND) 0 V dc Input high voltage (VIH) . 2.2 V dc minimum Input low voltage (VIL) . 0.8 V dc maximum Case operating temperature range (TC) -55C to +125C. 1/ When a thermal resistance

10、value is included in MIL-STD-1835, it shall supersede the value stated herein. 2/ Maximum junction temperature may be increased to +175C during burn-in and steady-state life tests. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT

11、 DRAWING SIZE A 5962-89661 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent sp

12、ecified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Stan

13、dard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mi

14、l/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in t

15、his document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Pr

16、oduct built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan an

17、d qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN

18、as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A an

19、d herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.2 Truth table. The truth table shall be as specified on figure 3. 3.2.3 Case outlines. The case outlines shall be in accordance with 1.2.2 and figure 1 herein. 3.3 Electrical performance characteris

20、tics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electri

21、cal tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89661 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 TABLE

22、 I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device types Limits Unit Min Max Output high voltage VOHVCC= 4.5 V, IOH= -4.0 mA VIN= VIH, VIL1, 2, 3 All 2.4 V Output low voltage VOLVCC= 4.5 V, IOL= 8.0

23、mA VIN= VIH, VIL1, 2, 3 All 0.4 V Input high voltage VIH2/ 1, 2, 3 All 2.2 V Input low voltage VIL2/ 1, 2, 3 All 0.8 V Input leakage current IIXVIN= 5.5 V to GND 1, 2, 3 All -10 +10 A DC supply current ICC1VCC= 5.5 V, IOUT= 0 mA VIN= 0 V and 3.0 V, f = 0 1, 2, 3 All 125 mA Operating supply current I

24、CC2VCC= 5.5 V, IOUT= 0 mA VIN= 0 V and 3.0 V 1, 2, 3 All 3/ A Input capacitance CINVCC= 5.0 V, TA = +25C, f = 1 MHz See 4.3.1c 4 All 8 pF Output capacitance COUTVCC= 5.0 V, TA = +25C, f = 1 MHz See 4.3.1c 4 All 8 pF Functional tests See 4.3.1d 7, 8 All Operating frequency fO4/ 9, 10, 11 01 15 MHz 02

25、 25 SI high time tPHSI4/ See figure 5 9, 10, 11 01 23 ns 02 11 SI low time tPLSI4/ 9, 10, 11 01 25 ns 02 24 Data setup to SI tSSI5/ 9, 10, 11 All 0 ns Data hold from SI tHSI5/ 9, 10, 11 01 30 ns 02 20 Delay, SI high to IR low tDLIR9, 10, 11 01 35 ns 02 21 Delay, SI low to IR high tDHIR9, 10, 11 01 4

26、0 ns 02 23 SO high time tPHSO4/ 9, 10, 11 01 23 ns 02 11 SO low time tPLSO4/ 9, 10, 11 01 25 ns 02 24 Delay, SO high to OR low tDLOR9, 10, 11 01 35 ns 02 21 Delay, SO low to OR high tDHOR9, 10, 11 01 40 ns 02 23 Data setup to OR high tSOR9, 10, 11 All 0 ns Data hold from SO low tHSO9, 10, 11 All 0 n

27、s See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89661 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical perfor

28、mance characteristics - continued. Test Symbol Conditions 1/ -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device types Limits Unit Min Max Fallthrough, bubbleback time tBTSee figure 5 9, 10, 11 01 10 65 ns 02 10 60 Data setup to IR tSIR6/ 9, 10, 11 All 5 ns Data hold fr

29、om IR tHIR6/ 9, 10, 11 01 30 ns 02 20 Input ready pulse high tPIR7/ 9, 10, 11 All 6 ns Output ready pulse high tPOR8/ 9, 10, 11 All 6 ns SI low to HF high tDHHF9, 10, 11 01 65 ns 02 55 SO low to HF low tDLHF9, 10, 11 01 65 ns 02 55 SO or SI low to AFE low tDLAFE9, 10, 11 01 65 ns 02 55 SO or SI low

30、to AFE high tDHAFE9, 10, 11 01 65 ns 02 55 MR pulse width tPMR9, 10, 11 01 55 ns 02 45 MR high to SI high tDSI9, 10, 11 01 25 ns 02 10 MR low to OR low tDOR9, 10, 11 01 55 ns 02 45 MR low to IR high tDIR9, 10, 11 01 55 ns 02 45 MR low to output low tLZMR9/ 9, 10, 11 01 55 ns 02 45 MR low to AFE high

31、 tAFE9, 10, 11 01 55 ns 02 45 MR low to HF low tHF9, 10, 11 01 55 ns 02 45 1/ AC tests are performed with input rise and fall times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 V to 3.0 V, and the output load on figure 4. 2/ These are absolute values with respect to dev

32、ice ground and all overshoots due to system or tester noise are included. 3/ Subgroups 1, 2, and 3 tests for ICC2shall be tested to the calculated limit for initial test and after any design or process changes which may affect this parameter. To calculate ICC2at any given operating frequency, use IC

33、C1+ (1 mA/MHz) x (1/fOSI+ 1/fOSO)/2. 4/ 1/fO (tPHSI+ tPLSI), 1/fO (tPHSO+ tPLSO). 5/ The parameters tSSIand tHSIapply when memory is not full. 6/ The parameters tSIRand tHIRapply when memory is full, SI is high and minimum bubblethrough (tBT) conditions exist. 7/ At any given operating condition tPI

34、R (tPHSOrequired). 8/ At any given operating condition tPOR (tPHSIrequired). 9/ All data outputs will be at low level after reset goes high until data is entered into the FIFO. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRA

35、WING SIZE A 5962-89661 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be

36、 marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in complia

37、nce to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in o

38、rder to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and

39、 the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required

40、 for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore

41、 at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quali

42、ty conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition D or E. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing activity upon

43、request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except i

44、nterim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional crite

45、ria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (COUTand CINmeasurements) shall be measured only for the initial test and after process or design changes which ma

46、y affect capacitance. Sample size is fifteen devices with no failures and all input and output terminals tested. d. Subgroups 7 and 8 shall test sufficient to verify the truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCU

47、IT DRAWING SIZE A 5962-89661 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883.

48、 (1) Test condition D or E. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA= +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. FIGURE 1.