DLA SMD-5962-89668 REV B-2006 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY TTL SYNCHRONOUS 8-BIT UP DOWN COUNTER WITH ASYNCHRONOUS CLEAR MONOLITHIC SILICON《硅单片 装有同步复位键的同步8位增值降值计数.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R340-97. 97-06-02 Raymond L. Monnin B Update to current requirements. Editorial changes throughout. gap 06-06-22 Raymond Monnin The original first page of this drawing has been replaced. REV SHET REV SHET REV S

2、TATUS REV B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Tim H. Noh DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Wm. J. Johnson COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AP

3、PROVED BY William K. Heckman MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, SYNCHRONOUS 8-BIT AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-07-26 UP/DOWN COUNTER WITH ASYNCHRONOUS CLEAR, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89668 SHEET

4、 1 OF 12 DSCC FORM 2233 APR 97 5962-EE334-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89668 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SC

5、OPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89668 01 K X Drawing number Device

6、type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54AS867 Synchronous 8-bit up/down counter with asynchronous clear 1.2.2 Case outline(s). The case outline(s

7、) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 flat L GDIP3-T24 or CDIP4-T24 24 dual-in-line 3 CQCC1-N28 28 square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix

8、 A. 1.3 Absolute maximum ratings. Supply voltage range -0.5 V dc minimum to +7.0 V dc maximum Input voltage range . -1.2 V dc at -18 mA to +7.0 V dc Storage temperature range . -65C to +150C Maximum power dissipation (PD) 1/ 1072.5 mW Lead temperature (soldering, 10 seconds) +300C Thermal resistance

9、, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) . +4.5 V dc minimum to +5.5 V dc maximum Maximum low-level input voltage (VIL) . +0.8 V dc Minimum high-level input voltage (VIH) +2 V dc Maximum high-level outpu

10、t current (IOH) . -2.0 mA Maximum low-level output current (IOL) . 20 mA _ 1/ Maximum power dissipation is defined as VCCx ICC, and the device must withstand the added PDdue to output current test; e.g., IO. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IH

11、S-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89668 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. - Continued. Case operating temperature range (TC) -55C to +125C Clock frequency range (fCLK) . 0 MHz to

12、 40 MHz Minimum clock pulse duration (tWCLK) . 12.5 ns Minimum clear pulse duration (S0 and S1 low) (tWCLR) . 12.5 ns Minimum skew time between S0 and S1 (maximum to avoid inadvertent clear), (tSKEW) . 8.0 ns Setup time (tS): 2/ Data inputs (A through H) 5.0 ns minimum Enable P ( ENP ) when changing

13、 from load 0s to count down for output, (QH) 23 ns minimum Enable P ( ENP ) when changing from load 0s to count down for output, (RCO) 21 ns minimum Enable P ( ENP ) (all other conditions) or Enable T (ENT ) . 9.0 ns minimum S0 to S1 (load) . 11 ns minimum S0 to S1 (clear) 11 ns minimum S0 to S1 (co

14、unt down) . 42 ns minimum S0 to S1 (count up) 42 ns minimum Hold time at any input with respect to CLK (th) 0.0 ns minimum 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent s

15、pecified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Sta

16、ndard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mi

17、l;quicksearch/ or www.dodssp.daps.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes p

18、recedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 2/ This setup time is required to ensure stable data. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD M

19、ICROCIRCUIT DRAWING SIZE A 5962-89668 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B device

20、s and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufactu

21、rers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modificati

22、ons shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in

23、 MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagra

24、m. The logic diagram shall be as specified on figure 3. 3.2.5 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics ar

25、e as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in

26、 accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not mark

27、ing the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-385

28、35 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listin

29、g as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of micr

30、ocircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applica

31、ble required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89668 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS,

32、 OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C Group A subgroups Limits Unit unless otherwise specified Min Max High level output voltage VOHVCC= 4.5 V, IOH= -2.0 mA, VIL= 0.8 V, VIH= 2.0 V 2/ 1

33、, 2, 3 2.5 V Low level output voltage VOL1VCC= 4.5 V, VIH= 2.0 V, RCO , VIL= 0.7 V 1, 2, 3 0.5 V VOL2IOL= 20 mA 2/ other outputs, VIL= 0.8 V 0.5 Input clamp voltage VICVCC= 4.5 V, IIN= -18 mA 1, 2, 3 -1.2 V Low level input current IILVCC= 4.5 V, VIN= 0.4 V ENT 1, 2, 3 -4.0 mA other inputs -2.0 High

34、level input current IIH1VCC= 5.5 V, VIN= 2.7 V ENT 1, 2, 3 40 A other inputs 20 Input current IIH2VCC= 5.5 V, VIN= 7.0 V 1, 2, 3 0.1 mA Output current IOVCC= 5.5 V, VOUT= 2.25 V 3/ 1, 2, 3 -30 -112 mA Supply current ICCVCC= 5.5 V 1, 2, 3 195 mA Functional tests See 4.3.1c 7, 8 Maximum clock frequenc

35、y fMAXVCC= 5.5 V, RL= 500, CL= 50 pF 4/ 9, 10, 11 40 MHz See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89668 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION

36、LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued Test Symbol Conditions 1/ -55C TC +125C Group A subgroups Limits Unit unless otherwise specified Min Max Propagation delay time, CLK to RCO tPLH1VCC= 4.5 V to 5.5 V, CL= 50 pF, 9, 10, 11 5.0 31 ns tPHL1

37、RL= 500 , see figure 4 5/ 6.0 19 Propagation delay time, CLK to any Q tPLH29, 10, 11 3.0 12 ns tPHL24.0 16 Propagation delay time, ENT to RCO tPLH39, 10, 11 3.0 19 ns tPHL35.0 21 Propagation delay time, ENP to RCO tPLH49, 10, 11 5.0 16 ns tPHL45.0 21 Propagation delay time, clear (S0, S1 low) to any

38、 Q tPLH59, 10, 11 7.0 23 ns 1/ Unused inputs that do not directly control the pin under test must be 2.5 V or 0.4 V. No unused inputs shall exceed 5.5 V or go less than 0.0 V. No inputs shall be floated. 2/ All outputs must be tested. In the case where only one input at VILmaximum or VIHminimum prod

39、uces the proper output state, the test must be performed with each input being selected as the VILmaximum or VIHminimum input. 3/ The output conditions have been chosen to produce a current that closely approximates one-half of the true short circuit output current, IOS. Not more than one output wil

40、l be tested at one time and the duration of the test condition shall not exceed 1 second. 4/ Maximum clock frequency, if not tested, shall guarantee to the limits specified in table I. 5/ Propagation delay time limits are based on single output switching. Unused inputs = 3.5 V or 0.3 V. Provided by

41、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89668 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Case outlines K and L 3 Terminal number Terminal symbol Termin

42、al symbol 1 S0 NC 2 S1 S0 3 A S1 4 B A 5 C B 6 D C 7 E D 8 F NC 9 G E 10 H F 11 ENT G 12 GND H 13 RCO ENT 14 CLK GND 15 QH NC 16 QG RCO 17 QF CLK 18 QE QH 19 QD QG 20 QC QF 21 QB QE 22 QA NC 23 ENP QD 24 VCCQC 25 - - - QB 26 - - - QA 27 - - - ENP 28 - - - VCCFIGURE 1. Terminal connections. Provided

43、by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89668 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Inputs Function ENP ENT S1 S0 X X L L Clear L L L H Count d

44、own X X H L Load L L H H Count up H = High voltage level L = Low voltage level X = Irrelevant FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89668 DEFENSE SUPPLY CENTER COLUMBUS COLUMB

45、US, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89668 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVIS

46、ION LEVEL B SHEET 10 DSCC FORM 2234 APR 97 NOTES: 1. CLincludes probe and jig capacitance. 2. All input pulses have the following characteristics: PRR 10 MHZ, duty cycle = 50 %, tr= tf= 3 ns 1 ns. 3. The outputs are measured one at a time with one input transition per measurement. FIGURE 4. Test cir

47、cuit and switching waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89668 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 11 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1

48、 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacture