DLA SMD-5962-89672 REV A-2001 MICROCIRCUIT LINEAR DUAL 12-BIT DOUBLE-BUFFERED MULTIPLYING CMOS DIGITAL-TO-ANALOG CONVERTER MONOLITHIC SILICON《硅单片 双重12位双缓冲多路复用氧化物半导体数字模拟转变器 线性微型电路》.pdf

1、REVISIONSLTR DESCRIPTION DATE (YR-MO-DA) APPROVEDA Drawing updated to reflect current requirements. - lgt 01-07-25 Raymond MonninTHE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED.REVSHEETREVSHEETREV STATUS REV AAAAAAAAAAAAOF SHETS SHET 12345678910112PMIC N/A PREPARED BY Rick C. OfficerDEFEN

2、SE SUPPLY CENTER COLUMBUSSTANDARDMICROCIRCUITDRAWINGCHECKED BYCharles ReusingCOLUMBUS, OHIO 43216http:/www.dscc.dla.milTHIS DRAWING IS AVAILABLEFOR USE BY ALLDEPARTMENTSAPPROVED BYMichael FryeMICROCIRCUIT, LINEAR, DUAL 12-BIT, DOUBLE-BUFFERED MULTIPLYING CMOS, DIGITAL-TO-ANALOG CONVERTER, MONOLITHIC

3、 SILICONAND AGENCIES OF THEDEPARTMENT OF DEFENSEDRAWING APPROVAL DATE03 November 1989AMSC N/AREVISION LEVELASIZEACAGE CODE672685962-89672SHEET1 OF 12DSCC FORM 2233APR 97 5962-E532-01DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo repro

4、duction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA5962-89672DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISION LEVELASHEET2DSCC FORM 2234APR 971. SCOPE1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN cla

5、ss level B microcircuits inaccordance with MIL-PRF-38535, appendix A.1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:5962-89672 01 L XDrawing number Device type(see 1.2.1)Case outline(see 1.2.2)Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s)

6、 identify the circuit function as follows:Device type Generic number Circuit function01 DAC-8222A Dual 12-bit double buffered multiplying CMOS digital-to-analog converter1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:Outline letter Descriptive designator

7、Terminals Package styleL GDIP3-T24 or CDIP4-T24 24 Dual-in-line1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.1.3 Absolute maximum ratings. VDD to AGND 0 V dc to +17.0 V dcVDD to DGND 0 V dc to +17.0 V dcAGND to DGND -0.3 V dc to VDD +0.3 V dcDigital input voltage to

8、 DGND -0.3 V dc to VDD +0.3 V dcIOUTA, IOUTB to AGND -0.3 V dc to VDD +0.3 V dcVREFA, VREFB to AGND G0125 V dcVoltage from RFBA, RFBB to AGND G0125 V dcPower dissipation (PD) to +75G02C. 500 mW 1/Ambient operating temperature range (TA) -55G02C to +125G02CDice junction temperature (TJ) . +150G02CSto

9、rage temperature -65G02C to +150G02CLead temperature (soldering, 60 s) +300G02CThermal resistance, junction-to-case (G03JC) . See MIL-STD-1835Thermal resistance, junction-to-ambient (G03JA) 150G02C/W1.4 Recommended operating conditions.Ambient operating temperature range (TA) -55G02C to +125G02CVREF

10、 G0110 VVOUTA, VOUTB . 0 VVDD +5 V or +15 V1/ Derate above 75G02C at 6.6 mW/G02C.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA5962-89672DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISION LEVELASHEET3DS

11、CC FORM 2234APR 972. APPLICABLE DOCUMENTS2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form apart of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listedin the issue of

12、the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited inthe solicitation.SPECIFICATIONDEPARTMENT OF DEFENSEMIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.STANDARDSDEPARTMENT OF DEFENSEMIL-STD-883 - Test Method Standard M

13、icrocircuits.MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.HANDBOOKSDEPARTMENT OF DEFENSEMIL-HDBK-103 - List of Standard Microcircuit Drawings.MIL-HDBK-780 - Standard Microcircuit Drawings.(Unless otherwise indicated, copies of the specification, standards, and handbooks are a

14、vailable from the StandardizationDocument Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the textof this drawing takes precedence. Nothing in this document

15、, however, supersedes applicable laws and regulations unless aspecific exemption has been obtained.3. REQUIREMENTS3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to

16、this drawing that is produced by a Qualified ManufacturerListing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifyingacti

17、vity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) planmay make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herei

18、n. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be asspecified in MIL-PRF-38535, appendix A and herein.3.2.1 Term

19、inal connections. The terminal connections shall be as specified on figure 1.3.2.2 Truth table. The truth table shall be as specified on figure 2.3.2.3 Functional diagram. The functional diagram shall be as specified on figure 3.3.2.4 Case outline. The case outline shall be in accordance with 1.2.2

20、herein.3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics areas specified in table I and shall apply over the full ambient operating temperature range.3.4 Electrical test requirements. The electrical test requirements shall be th

21、e subgroups specified in table II. The electricaltests for each subgroup are described in table I.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA5962-89672DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISI

22、ON LEVELASHEET4DSCC FORM 2234APR 973.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PINlisted in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). Forpackages where marking of the

23、 entire SMD PIN number is not feasible due to space limitations, the manufacturer has theoption of not marking the “5962-“ on the device.3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in complianceto MIL-PRF-38535, appendix A. The complia

24、nce indicator “C” shall be replaced with a “Q“ or “QML“ certification mark inaccordance with MIL-PRF-38535 to identify when the QML flow option is used.3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as anapproved source of suppl

25、y in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior tolisting as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein.3.7 Certificate of conformance. A certifi

26、cate of conformance as required in MIL-PRF-38535, appendix A shall be providedwith each lot of microcircuits delivered to this drawing.3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535,appendix A.3.9 Verification and review. DSCC, DSCCs

27、agent, and the acquiring activity retain the option to review the manufacturersfacility and applicable required documentation. Offshore documentation shall be made available onshore at the option of thereviewer.4. QUALITY ASSURANCE PROVISIONS4.1 Sampling and inspection. Sampling and inspection proce

28、dures shall be in accordance with MIL-PRF-38535,appendix A.4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devicesprior to quality conformance inspection. The following additional criteria shall apply:a. Burn-in test, method 1015 of MIL-

29、STD-883.(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision levelcontrol and shall be made available to the preparing or acquiring activity upon request. The test circuit shallspecify the inputs, outputs, biases, and power dissipation, a

30、s applicable, in accordance with the intent specified intest method 1015 of MIL-STD-883.(2) TA = +125G02C, minimum.b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parametertests prior to burn-in are optional at the discretion of the

31、 manufacturer.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA5962-89672DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISION LEVELASHEET5DSCC FORM 2234APR 97TABLE I. Electrical performance characteristics.T

32、est SymbolConditions-55G02C G04 TA G04+125G02CVOUTA = VOUTB = 0 VVDD = +5 V or +15 VVREF = G0110 Vunless otherwise specifiedGroup AsubgroupsDevicetypeLimits UnitMin MaxRelative accuracy INL 1, 2, 3 01 G010.5 LSBDifferentialnonlinearityDNL 1, 2, 3 01 G011.0 LSBGain error GFSE1, 2, 3 01 G011.0 LSBDC p

33、ower supplyrejection DDVGainG05G051/PSRR 1, 2, 3 01 0.002%Output leakagecurrentIOUTA, IOUTB 2/ILKG 101 G0110 nA2, 3 G0150Input resistance RIN1, 2, 3 01 8 15 kG06Input resistancematchG05RREF 1, 2, 3 01 G011.0 %Digital input high VIH VDD = +5 V1, 2, 3 01 2.4 VVDD = +15 V 13.5Digital input low VIL VDD

34、= +5 V1, 2, 3 01 0.8 VVDD = +15 V 1.5Input current IIN VIN = 0 V or VDD101 G011.0 G07A2, 3 G0110.0Supply current IDD Digital inputs VINL or VINH1, 2, 3 01 2.0 mADigital inputs 0 V or VDD 0.1Input capacitance CIN Measuring at DB0 DB11pins, see 4.3.1c401 10pFMeasuring at WR , LDAC ,DACA / DAC B pins,s

35、ee4.3.1c15Functional test See 4.3.1d 7, 8DAC select to writesetup time 3/tAS VDD = +5 V 9 01 150 nsVDD = +15 V 60VDD = +5 V 10, 114/210VDD = +15 V 60See footnotes at end of table.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DR

36、AWINGSIZEA5962-89672DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISION LEVELASHEET6DSCC FORM 2234APR 97TABLE I. Electrical performance characteristics - Continued.Test SymbolConditions-55G02C G04 TA G04+125G02CVOUTA = VOUTB = 0 VVDD = +5 V or +15 VVREF = G0110 Vunless otherwise specifie

37、dGroup AsubgroupsDevicetypeLimits UnitMin MaxDAC select to writehold time 3/ 4/tAH 9, 10, 11 01 0 nsLDAC to write setuptime 3/tLS VDD = +5 V 90180 nsVDD = +15 V 60VDD = +5 V 10, 114/120VDD = +15 V 60LDAC to write holdtime 3/tLH 90120 ns10, 114/10Data valid to writesetup time 3/tDS VDD = +5 V 9 01 22

38、0 nsVDD = +15 V 100VDD = +5 V 10, 114/260VDD = +15 V 100Data valid to writehold time 3/ 4/tDH VDD = +5 V 9, 10, 11 01 0 nsVDD = +15 V 10Write pulse width 3/ tWR VDD = +5 V9 01 130 nsVDD = +15 V 90VDD = +5 V 10, 114/170VDD = +15 V 90LDAC pulse width 3/ tLWD VDD = +5 V9 01 100 nsVDD = +15 V 60VDD = +5

39、 V 10, 114/130VDD = +15 V 601/ G05VDD = G015%.2/ DAC loaded with 0000 0000 0000.3/ See figure 4.4/ Subgroups 10 and 11, if not tested, shall be guaranteed to the limits specified in table I.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICR

40、OCIRCUIT DRAWINGSIZEA5962-89672DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISION LEVELASHEET7DSCC FORM 2234APR 974.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The fo

41、llowing additional criteria shall apply.4.3.1 Group A inspection.a. Tests shall be as specified in table II herein.b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.c. Subgroup 4 (CIN measurement) shall be measured only for the initial test and after process or design chan

42、ges whichmay affect input capacitance.d. Subgroups 7 and 8 shall include verification of the truth table.4.3.2 Groups C and D inspections.a. End-point electrical parameters shall be as specified in table II herein.b. Steady-state life test conditions, method 1005 of MIL-STD-883.(1) Test condition A,

43、 B, C, or D. The test circuit shall be maintained by the manufacturer under document revisionlevel control and shall be made available to the preparing or acquiring activity upon request. The test circuitshall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance w

44、ith the intentspecified in test method 1005 of MIL-STD-883.(2) TA = +125G02C, minimum.(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.5. PACKAGING5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A.Provide

45、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGSIZEA5962-89672DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISION LEVELASHEET8DSCC FORM 2234APR 97Device type 01Case outline LTerminal number Terminal symbol1AGND2 IOUT

46、A3 RFBA4 VREFA5DGND6DB11(MSB)7 DB108 DB99 DB810 DB711 DB612 DB513 DB414 DB315 DB216 DB117 DB0(LSB)18DACA / DAC B19LDAC20WR21 VDD22 VREFB23 RFBB24 IOUTBFIGURE 1. Terminal connections.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT

47、 DRAWINGSIZEA5962-89672DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISION LEVELASHEET9DSCC FORM 2234APR 97Digital inputs DAC register statusDAC A DAC BDACA / DAC B WRLDAC INPUTLATCHDACLATCHINPUTLATCHDACLATCHL L L WRITE WRITE LATCHED WRITEH L L LATCHED WRITE WRITE WRITEL L H WRITE LATCHE

48、D LATCHED LATCHEDH L H LATCHED LATCHED WRITE LATCHEDX H L LATCHED WRITE LATCHED WRITEX H H LATCHED LATCHED LATCHED LATCHEDL = LowH = HighX = Dont careFIGURE 2. Truth table.FIGURE 3. Functional diagram.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-S

49、TANDARDMICROCIRCUIT DRAWINGSIZEA5962-89672DEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000REVISION LEVELASHEET10DSCC FORM 2234APR 97THREE CYCLE UPDATENOTES:1. All input signal rise and fall times measured from 10% to 90% of VDDVDD = +5 V, tr = tf = 20 ns;VDD = +15 V, tr = tf = 40 ns.2. Timing me