DLA SMD-5962-89674 REV D-2012 MICROCIRCUIT LINEAR CMOS 14-BIT ANALOG-TO-DIGITAL CONVERTER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add device type 02. Made changes to table I, figure 1, figure 3, and figure 4. Editorial changes throughout. 90-06-28 Monica L. Poelking B Changes in accordance with NOR 5962-R083-94. 94-03-24 Michael A. Frye C Drawing updated to reflect current

2、requirements. - lgt 01-08-23 Raymond Monnin D Redraw. Paragraphs updated to the latest MIL-PRF-38535 requirements. -drw 12-10-11 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV SHEET REV STATUS REV D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8

3、9 10 11 12 13 PMIC N/A PREPARED BY Rick C. Officer DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Charles E. Besore APPROVED BY M

4、ichael A. Frye MICROCIRCUIT, LINEAR, CMOS, 14-BIT ANALOG-TO-DIGITAL CONVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-08-04 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-89674 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E006-13 Provided by IHSNot for ResaleNo reproduction or networking per

5、mitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89674 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcirc

6、uits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89674 01 X A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device types. The device types identify the

7、circuit function as follows: Device type Generic number Circuit function INL test 01 5014-S 14-bit CMOS analog-to-digital converter, 14.25 s 1.5 LSB 02 5014-T 14-bit CMOS analog-to-digital converter, 14.25 s 0.5 LSB 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as foll

8、ows: Outline letter Descriptive designator Terminals Package style Q GDIP1-T40 or CDIP2-T40 40 Dual-in-line X CQCC1-N44 44 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Positive digital supply voltage ra

9、nge (+VD) . -0.3 V dc to +6.0 V dc 2/ Negative digital supply voltage range (-VD) +0.3 V dc to -6.0 V dc Positive analog supply voltage range (+VA) . -0.3 V dc to +6.0 V dc Negative analog supply voltage range (-VA). +0.3 V dc to -6.0 V dc Analog ground (AGND) to digital ground (DGND) 0.5 V dc Input

10、 current, any pin except supplies 10 mA 3/ Analog input voltage (AIN and VREFpins) . -VA- 0.3 V dc to +VA+0.3 V dc Digital input voltage range -0.3 V dc to +VD+0.3 V dc Storage temperature range -65C to +150C Lead temperature (soldering, 10 seconds) . +260C Junction temperature (TJ). +195C Power dis

11、sipation (PD): Case Q 1500 mW Case X 1100 mW Thermal resistance, junction to case (JC) See MIL-STD-1835 Thermal resistance, junction to ambient (JA) Case Q 45C/W Case X 60C/W _ 1/ All voltages referenced to AGND and DGND tied together. 2/ In addition +VDmust not be greater than +VA+ 0.3 V dc. 3/ Tra

12、nsient currents of up to 100 mA will not cause latch-up. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89674 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.

13、4 Recommended operating conditions. 1/ Ambient operating temperature range (TA) -55C to +125C Positive digital supply voltage (+VD) . +4.5 V dc to +VAV dc 2/ Negative digital supply voltage (-VD) -4.5 V dc to -5.5 V dc Positive analog supply voltage (+VA) . +4.5 V dc to +5.5 V dc Negative analog sup

14、ply voltage (-VA) . -4.5 V dc to -5.5 V dc Digital ground (DGND) . 0 V dc Analog ground (AGND) 0 V dc Digital input low voltage (VIL) -0.3 V dc to +0.8 V dc Digital input high voltage (VIH) +2.0 V dc to +VDAnalog reference input voltage (VREF) range +4.5 V dc Analog input voltage range: Unipolar mod

15、e AGND to +VREFBipolar mode -VREFto +VREF2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are tho

16、se cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case O

17、utlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Bu

18、ilding 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific ex

19、emption has been obtained. _ 1/ All voltages referenced to AGND and DGND tied together. 2/ In addition +VDmust not be greater than +VA+ 0.3 V dc. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89674 DLA LAND

20、 AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawin

21、g that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity appr

22、oval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“

23、 or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outli

24、nes. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Block diagram. The block diagram shall be as specified on figure 3. 3.3

25、 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgro

26、ups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages wher

27、e marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appe

28、ndix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an ap

29、proved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein.

30、 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that aff

31、ects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the re

32、viewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89674 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Te

33、st Symbol Conditions -55C TA+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Resolution for which no missing codes is guaranteed RES 1/ 1, 2, 3 All 14 Bits Integral linearity error INL 1/, 2/ 1, 2, 3 01 1.5 LSB 02 0.5 Differential linearity error DNL 1/, 2/ 1, 2, 3

34、All 0.5 LSB Full-scale error FSE 1/, 2/ 1, 2, 3 All 1.0 LSB Full-scale error drift dFSE/dt1/, 2/, 3/, 4/ 2, 3 All 1.0 LSB Unipolar offset error VOFF 1/, 2/ 1, 2, 3 01 1.0 LSB 02 0.75 Unipolar offset error drift dVOFF/dt1/, 2/, 3/, 4/ 2, 3 All 0.5 LSB Bipolar offset error BOFF 1/, 2/ 1, 2, 3 01 1.0 L

35、SB 02 0.75 Bipolar offset error drift dBOFF/dt1/, 2/, 3/, 4/ 2, 3 All 1.0 LSB Bipolar negative full-scale error BNFSE 1/, 2/ 1, 2, 3 01 1.5 LSB 02 1.0 Bipolar negative full-scale error drift dBNFSE/dt1/, 2/, 3/, 4/ 2, 3 All 1.0 LSB Peak harmonic or spurious noise S/PN 1 kHz input, full scale amplitu

36、de, bipolar mode 1/, 2/ 4, 5, 6 01 85 dB 02 94 12 kHz input, full scale amplitude, bipolar mode 1/, 2/ 01 80 02 84 Analog input capacitance in fine charge mode CINUnipolar mode, TA= +25C 1/, 3/ 4 All 375 pF Bipolar mode, TA= +25C 1/, 3/ 220 Signal to noise ratio S/(N+D) 4, 5, 6 01 80 dB 02 82 See fo

37、otnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89674 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance ch

38、aracteristics - continued. Test Symbol Conditions -55C TA+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Digital input voltage ( HOLD , CLKIN, CAL, VIH5/, 6/ 1, 2, 3 All 2.0 V INTRLV , BW, RST, UPBP , AO, RD, CS) VIL0.8 Digital input current IIN5/, 6/ 1, 2, 3 All 1

39、0 A Digital output voltage VOLLogic “0”, ISINK= -1.6 mA 5/, 6/ 1, 2, 3 All 0.4 V (D0 D15, SDATA, SCLK, EOC , EOT ) VOHLogic “1”, ISOURCE= 100 A 5/, 6/ +VD -1.0 High impedance state output current IZPins D0to D15only 5/, 6/ 1, 2, 3 All 10 A Conversion time tC1/, 6/, 7/ 9, 10, 11 All 14.25 s Acquisiti

40、on time tACQTA= +25C 1/, 2/, 3/, 8/ 9 All 3.75 s Throughput tPUT1/, 6/, 7/ 9, 10, 11 All 55.6 kHz Positive analog supply current +IA+VA, +VD= 5.5 V, 6/, 9/ -VA, -VD= -5.5 V 1, 2, 3 All 19.0 mA Negative analog supply current -IA+VA, +VD= 5.5 V, 6/, 9/ -VA, -VD= -5.5 V 1, 2, 3 All 19.0 mA Positive dig

41、ital supply current +ID+VA, +VD= +5.5 V, 6/, 9/ -VA, -VD= -5.5 V 1, 2, 3 All 6.0 mA Negative digital supply current -ID+VA, +VD= +5.5 V, 6/, 9/ -VA, -VD= -5.5 V 1, 2, 3 All 6.0 mA Master clock frequency 10/ fCLKTA= -55C, Internally generated CLKIN = 0 V dc, +VD, +VA= +4.5 V, -VD, -VA= -4.5 V 11 All

42、1.75 MHz HOLD pulse width tHPWSee figure 4 5/, 6/, 11/ 9, 10, 11 All 1/fCLK +50 tCns Data delay time tDDSee figure 4 5/, 6/, 11/ 9, 10, 11 All 100 ns EOC pulse width tEPWSee figure 4 5/, 6/, 11/ 9, 10, 11 All 4/fCLK -20 ns CAL, INTRLV to CS low setup time tCSSee figure 5 5/, 6/, 11/ 9, 10, 11 All 20

43、 ns See footnotes at end of table Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89674 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical perfo

44、rmance characteristics - continued. Test Symbol Conditions -55C TA+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max A0 to CS and RD low setup time tASSee figure 5 5/, 6/, 11/ 9, 10, 11 All 20 ns CS or RD High to A0 invalid hold time tAHSee figure 5 5/, 6/, 11/ 9, 10,

45、 11 All 50 ns CS High to CAL, INTRLV invalid hold time tCHSee figure 5 5/, 6/, 11/ 9, 10, 11 All 50 ns CS low to data valid access time tCARD = logic “0”, see figure 5 5/, 6/, 11/ 9, 10, 11 All 150 ns RD low to data valid access time tRACS = logic “0”, see figure 5 5/, 6/, 11/ 9, 10, 11 All 150 ns O

46、utput float delay tFDSee figure 5 5/, 6/, 11/ 9, 10, 11 All 140 ns SDATA to SCLK rising setup time tSSSee figure 6 5/, 6/, 11/ 9, 10, 11 All 2/fCLK -50 ns SCLK rising to SDATA hold time tSHSee figure 6 5/, 6/, 11/ 9, 10, 11 All 2/fCLK -100 ns 1/ +VA, +VD= +5.0 V; -VA, -VD= - 5.0 V; VREF= +4.5 V dc;

47、fCLK= 4 MHz; analog source impedance = 200; error tests are done after calibration at the temperature of interest. 2/ Synchronous sampling mode (EOT connected to HOLD ), interleave disabled. 3/ This parameter shall be measured only for initial characterization and after process or design changes whi

48、ch may affect this parameter. 4/ Total drift over -55C to +125C since calibration at power-up at +25C. 5/ +VA, +VD= +5.0 V dc 10%; -VA, -VD= -5.0 V dc 10%. 6/ This parameter is guaranteed, if not tested, at TA= +25C. This parameter is tested at TA= -55C and +125C. 7/ Measured from falling transition on HOLD to falling transition on EOC . 8/ Acquisition time is the time allowed by the converter for acquisition of the input voltage prior to conversion. 9/ All outputs unloaded; All inputs swinging between -VDand 0