DLA SMD-5962-89681 REV D-2006 MICROCIRCUIT LINEAR OCTAL GENERAL INTERFACE BUS TRANSCEIVER MONOLITHIC SILICON《硅单片 总线收发器八位总接口 线性微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes to recommended operating conditions and table I. Editorial changes throughout. 95-05-10 M. A. Frye B Changes in accordance with NOR 5962-R123-96. 96-05-10 M. A. Frye C Changes in accordance with NOR 5962-R056-97. 96-10-31 Raymond Monnin D

2、 Update drawing to current requirements. Incorporate NOR revisions A and B. Editorial changes throughout. - drw 06-01-09 Raymond Monnin THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV SHET REV STATUS REV D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC

3、 N/A PREPARED BY Rick C. Officer DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles E. Besore COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, OCTAL GENERAL INTERFACE B

4、US TRANSCEIVER, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-08-23 MONOLITHIC SILICON AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-89681 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E177-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without licens

5、e from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89681 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in acco

6、rdance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89681 01 R A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type. The device type identifies the circuit functio

7、n as follows: Device type Generic number Circuit function 01 55ALS161 Octal general purpose interface bus transceiver 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 dual-in

8、 line S GDFP2-F20 or CDFP3-F20 20 flat pack 2 CQCC1-N20 20 square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage (VCC) +7.0 V dc Input voltage +5.5 V dc Low level driver output current. 100 mA Contin

9、uous total dissipation TA +25C 1/ 1375 mW Storage temperature range -65C to +150C Lead temperature (soldering, 10 seconds) +300C Junction temperature (TJ) +150C 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.75 V dc min to +5.25 V dc max Minimum high level input voltage (VIH): T

10、E and DC, TA= -55C to +125C . 2.0 V dc Bus and terminal, TA= +25C, +125C 2.0 V dc Bus and terminal, TA= -55C . 2.1 V dc Maximum low level input voltage (VIL): TE and DC, TA= -55C to +125C . 0.8 V dc Bus and terminal, TA= -55C, +25C . 0.8 V dc Bus and terminal, TA= +125C 0.7 V dc Maximum high level o

11、utput current (IOH): Bus ports with pull-ups active (VCC= 5.0 V dc) -5.2 mA Terminal ports -800 A Maximum low level output current (IOL): Bus ports, TA= +25C, +125C 48 mA Bus ports, TA= -55C. 24 mA Terminal ports 16 mA Ambient operating temperature range (TA) -55C to +125C _ 1/ For operation above T

12、A= +25C, derate at the rate of 11.0 mW/C.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89681 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 2. APPLIC

13、ABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTME

14、NT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-

15、103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philad

16、elphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been

17、obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qu

18、alified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Qua

19、lity Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to

20、identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Termin

21、al connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and

22、shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38

23、535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the devi

24、ce. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML

25、 flow option is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89681 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performa

26、nce characteristics. Test Symbol Conditions -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxHigh level output voltage (terminal) VOH1/ VCC= 4.75 V, IOH= -800 A 1, 2 01 2.7 V 3 2.5 High level output voltage (bus) 2/ VCC= 4.75 V, IOH= -5.2 mA 1, 2 2.5 3 2.0 Lo

27、w level output voltage (terminal) VOLVCC= 4.75 V, IOL= 16 mA 1, 2, 3 01 0.5 V Low level output voltage (bus) 2/ VCC= 4.75 V, IOL= 48 mA 1, 2 0.5 CC= 4.75 V, IOL= 24 mA 3 0.55 Input clamp voltage VIC VCC= 4.75 V, II= -18 mA 1, 2, 3 01 -1.5 V Bus hysteresis (VT+- VT-) VHYSVCC= 5 V 1, 3 01 0.4 V 2 0.25

28、 Voltage at bus port (driver disabled) VI/O(bus) II(bus) = 0 mA, VCC= 5 V 1, 2, 3 01 2.5 3.7 V I(bus) = -12 mA, VCC= 5 V -1.5 Current into bus port (power on, driver disabled) II/O(bus) VI(bus) = -1.5 V to 0.4 V, VCC= 5 V 1, 2, 3 01 -1.3 mA VI(bus) = 0.4 V to 2.5 V, VCC= 5 V 0 -3.2 VI(bus) = 2.5 V t

29、o 3.7 V, VCC= 5 V +2.5 -3.2 VI(bus) = 3.7 V to 5 V, VCC= 5 V 0 2.5 VI(bus) = 5 V to 5.5 V, VCC= 5 V 0.7 2.5 Current into bus port (power off) VI(bus) = 0.0 V to 2.5 V, VCC= 0.0 V 40 A High level input current (terminal, control inputs) IIH1VI= 2.7 V, VCC= 5.25 V 1, 2, 3 01 20 A Input current at maxi

30、mum input voltage (terminal) IIH2VI= 5.5 V, VCC= 5.25 V 1, 2, 3 01 100 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89681 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 4321

31、8-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxLow level input current (terminal, control inputs) IILVI= 0.5 V, VCC= 5.

32、25 V 1, 2, 3 01 -100 A Low level input current (ATN) VI= 0.5 V, VCC= 5.25 V -200 Short circuit output current (terminal) IOS1/ VCC= 5.25 V 1, 2, 3 01 -15 -75 mA Short circuit output current (bus) -25 -125 Supply current ICCVCC= 5.25 V, no load, TE and DC low 1, 2, 3 01 90 mA Functional tests FT See

33、4.3.1c 3/ 7, 8 01 tPLH19 01 17 ns Propagation delay time, from terminal to bus except SRQ, NDAC and NRFD VCC= 4.75 V to 5.25 V, R1= R2= 500, CL= 50 pF, See figure 3 10, 11 20 tPHL19 14 10, 11 16 Propagation delay time, from bus to terminal tPLH29 01 15 ns 10, 11 18 tPHL29 17 10, 11 21 tPLH39 01 25 n

34、s Propagation delay time, from terminal to bus SRQ, NDAC and NRFD 10, 11 30 tPHL39 14 10, 11 16 tPZH19 01 30 ns Output enable time, from TE to DC to bus ATN, REN, IFC and DAV 10, 11 45 tPZL19 28 10, 11 37 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permi

35、tted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89681 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions -55C TA +125C unless otherwise

36、 specified Group A subgroups Device type Limits Unit Min MaxtPHZ1 9 01 14 ns Output disable time, from TE or DC to bus ATN, REN, IFC and DAV VCC= 4.75 V to 5.25 V, R1= R2= 500, CL= 50 pF, See figure 3 10, 11 16 tPLZ1 9 19 10, 11 24 Output enable time, from TE or DC to terminal tPZH2 9 01 36 ns 10, 1

37、1 55 tPZL2 9 34 10, 11 46 Output disable time, from TE or DC to terminal tPHZ2 9 01 20 ns 10, 11 36 tPLZ2 9 24 10, 11 38 Output enable time, from TE or DC to bus EOI tPZH3 9 01 30 ns 10, 11 53 tPZL3 9 35 10, 11 45 Output disable time, from TE or DC to bus EOI tPHZ3 9 01 19 ns 10, 11 25 tPLZ3 9 20 10

38、, 11 33 1/ VOHand IOSapplies for three state outputs only. 2/ May not meet IEEE 488 standard. 3/ Functional test shall be conducted at input test conditions of GND VIL VOLand VOH VIH VCC. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICRO

39、CIRCUIT DRAWING SIZE A 5962-89681 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines R, S, and 2 Terminal number Terminal symbol 1 TE 2 REN 3 IFC 4 NDAC 5 NRFD 6 DAV 7 EOI 8 ATN 9 SRQ 10 GND 11 DC 12 SRQ 13 ATN 14 EOI

40、15 DAV 16 NRFD 17 NDAC 18 IFC 19 REN 20 VCCPin assignment Name Identity class DC Direction control TE Talk enable Control ATN Attention SRQ Service request REN Remote enable IFC Interface clear Bus management EOI End or Identity DAV Data valid NDAC Not data accepted NRFD Not ready for data Data tran

41、sfer Pin identification table FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89681 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM

42、2234 APR 97 Controls Bus-management channels Data-transfer channels DC TE ATN* ATN* SRQ REN IFC EOI DAV NDAC NRFD (Controlled by DC) (Controlled by TE) H H H R T R R T T R R H H L R L L H T R T T R R T T L L L T H L X R T R R R R T T L H X T R T T T T R R NOTE: H = High, L = Low, R = Receive, T = Tr

43、ansmit, X = Irrelevant Direction of data transmission is from the terminal side to the bus side and the direction of data receiving is from the bus side to the terminal side. Data transfer is noninverting in both directions. * ATN is a normal transceiver channel that functions additionally as an int

44、ernal direction control or talk enable for EOI whenever the DC and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only. FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without

45、 license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89681 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 NOTES: 1. The input pulse is supplied by a generator having the following characteristics, PRR 1.0 MHz, 50 percent duty cycle,

46、 tr 6 ns, tf ns, ZOUT= 50. 2. CLincludes probe and jig capacitance. FIGURE 3. Test circuits and voltage waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89681 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS

47、, OHIO 43218-3990 REVISION LEVEL D SHEET 10 DSCC FORM 2234 APR 97 NOTES: 1. The input pulse is supplied by a generator having the following characteristics, PRR 1.0 MHz, 50 percent duty cycle, tr 6 ns, tf ns, ZOUT= 50. 2. CLincludes probe and jig capacitance. FIGURE 3. Test circuits and voltage wave

48、forms - continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89681 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 11 DSCC FORM 2234 APR 97 3.6 Certificate of compliance. A certificate of compliance shall be required from a ma