DLA SMD-5962-89690 REV A-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 2K X 8 STATIC RAM (SRAM) MONOLITHIC SILICON《硅单片 2K X 8 静态随机存取存储器 氧化物半导体数字记忆微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Boilerplate update, part of 5 year review. ksr 06-10-26 Raymond Monnin THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV SHET REV STATUS REV A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A P

2、REPARED BY Kenneth S. Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPRO

3、VAL DATE 89-10-16 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 8 STATIC RAM (SRAM), MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-89690 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E009-07 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

4、IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89690 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance

5、with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89690 01 J A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function a

6、s follows: Device type Generic number Circuit function Acess time 01 1/ 2K X 8 CMOS SRAM 25 ns 02 1/ 2K X 8 CMOS SRAM 20 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style J GDIP1-T24 or CDIP2-

7、T24 24 dual-in-line package K GDFP2-F24 or CDFP3-F24 24 flat package L GDIP3-T24 or CDIP4-T24 24 dual-in-line package X CQCC1-N32 32 rectangular chip carrier package Y See Figure 1 24 rectangular chip carrier package Z CQCC3-N28 28 rectangular chip carrier package 3 CQCC1-N28 28 rectangular chip car

8、rier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 2/ Supply voltage range (VCC) - -0.5 V dc to 7 V dc Input voltage range 2/ - 0.5 V to VCC+0.5 V Output voltage range in high impedance state - -0.5 V dc to 7 V dc Output curren

9、t- 20 mA Storage temperature range- -65C to +150C Power dissipation, (PD) - 864 mW Lead temperature (soldering, 10 seconds) - +275C Junction temperature (TJ) - +175C Thermal resistance, junction-to-case (JC):. Cases J, K, L, X, Z, and 3- See MIL-STD-1835 Case Y- 20C/W 1.4 Recommended operating condi

10、tions. Supply voltage range (VCC) - 4.5 V dc minimum to 5.5 V dc maximum High level Input voltage range (VIH) - 2.2 V dc minimum to VCC+ 0.5 V dc maximum Low level Input voltage range (VIL) 3/ - -0.5 V dc minimum to 0.8 V dc maximum Case operating temperature range (TC)- -55C to +125C 1/ Generic num

11、bers are listed on the Standardized Military Drawing Source Approval Bulletin at the end of this document and will also be listed in MIL-HDBK-103. 2/ All voltages are with respect to GND. 3/ VIL(minimum) of -3 V dc for short pulse durations of 20 ns or less. Prolonged operation at VILlevels below -1

12、 V dc will result in excessive currents that may damage the device. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89690 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC

13、 FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicit

14、ation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF

15、DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins

16、Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a s

17、pecific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Lis

18、ting (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML fl

19、ow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MI

20、L-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as s

21、pecified on figure 2. 3.2.2 Truth table. The truth table shall be as specified on figure 3. 3.2.3 Case outlines. The case outlines shall be in accordance with 1.2.2 herein and figure 1. 3.2.4 Load circuit and switching waveforms. The load circuit and switching waveforms shall be as specified on figu

22、re 4. 3.2.5 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only. Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the internal moisture content test at 5000 ppm

23、 (see method 1018 of MIL-STD-883). The frequency of the internal water vapor testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the requirements as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal. 3.3

24、Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups

25、specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89690 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION

26、LEVEL A SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions Group A Device Unit -55C (VCC-0.2 V) Input leakage current, IILKVCC= 5.5 V, 1,2,3 All -10 10 A any input VIN= 0 V to 5.5 V, Off-state output leakage IOLKVCC= 5.5 V 1,2,3 All -10 10 A

27、current VIN= 0 V to 5.5 V, Output high voltage VOH IOUT= -4.0 mA, VCC= 4.5 V, 1,2,3 All 2.4 V VIL= 0.8 V, VIH= 2.2 V Output low voltage VOL IOUT= 8 mA, VCC= 4.5 V, 1,2,3 All 0.4 V VIL= 0.8 V, VIH= 2.2 V Input capacitance 5/ CINVIN= 0 V, 4 All 8 pF f = 1.0 Mhz, TA= +25C, see 4.3.1c Output capacitance

28、 5/ COUTVOUT= 0 V, 4 All 8 pF f = 1 Mhz, TA= +25C, see 4.3.1c Read cycle time tAVAV 9, 10 11 01 25 ns 02 20 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89690 DEFENSE SUPPLY

29、CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions Group A Device Unit -55C TC +125C subgroups type Min Max 4.5 V VCC 5.5 V VSS= 0 V unless otherwise specified 1/ 2/ 3/ 4/

30、 Address access time tAVQV 9, 10, 11 01 25 ns 02 20 Output hold after address tAVQX 9, 10, 11 01 0 ns change 02 0 Output enable to output tOLQX 9, 10, 11 01 0 ns active 5/ 6/ 02 0 Output enable access tOLQV 9, 10, 11 01 16 ns time 02 15 Chip enable to output tELQX 9, 10, 11 01 0 ns active 5/ 6/ 02 0

31、 Chip enable access time tELQV 9, 10, 11 01 25 ns 02 20 Chip enable to output tEHQZ 9, 10, 11 01 15 ns in high Z 5/ 6/ 02 15 Write recovery time tWHAV 9, 10, 11 01 0 ns 02 0 Chip enable to end of tELWH 9, 10, 11 01 20 ns write 02 15 Address valid to end of tAVWH 9, 10, 11 01 20 ns write 02 15 Addres

32、s to WE setup time tAVWL 9, 10, 11 01 0 ns 02 0 Address to CE setup time tAVEL 9, 10, 11 01, 02 0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89690 DEFENSE SUPPLY CENTER

33、COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions Group A Device Unit -55C TC +125C subgroups type Min Max 4.5 V VCC 5.5 V VSS= 0 V unless otherwise specified 1/ 2/ 3/ 4/ Output

34、 enable to output tOHQZ 9, 10, 11 01 16 ns in high Z 5/ 6/ 02 15 Write enable pulse width tWLWH 9, 10, 11 01 20 ns 02 15 Data setup to end of write tDVWH 9, 10, 11 01 15 ns 02 12 Data hold after end of writetWHDX 9, 10, 11 01 0 ns 02 0 Chip enable pulse width tELEH 9, 10, 11 01 20 ns during write 02

35、 15 Write enable pulse setup tWLEH 9, 10, 11 01 20 ns time 02 15 Write enable to output tWLQZ 9, 10, 11 01 15 ns in high Z 5/ 6/ 02 15 1/ All voltages referenced to VSS. 2/ Negative undershoots to a minimum of -0.3 V are allowed with a maximum of 50 ns pulse width. 3/ AC measurements assume transiti

36、on time 5 ns and input level are from VSSto 3.0 V. Output load is specified on figure 4. Reference timing levels are 1.5 V. 4/ For timing waveforms, see figure 4. 5/ Tested initially and after any design and or process changes which may affect this parameters, and therefore shall be guaranteed to th

37、e limits specified in table I. Transition measured 500 mV from steady-state value. 6/ This parameter measured 500 mV from steady-state output voltage. Load capacitance is 5.0 pF, see figure 4. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the devi