DLA SMD-5962-89697 REV C-2013 MICROCIRCUIT LINEAR 16-BIT VOLTAGE OUTPUT DAC MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R057-92. 91-11-18 Michael A. Frye B Drawing updated to reflect current requirements. - lgt 01-12-07 Raymond Monnin C Redrawn. Paragraphs updated to MIL-PRF-38535 requirements. - drw 13-07-18 Charles F. Saffle T

2、HE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV SHEET REV STATUS REV C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Rick C. Officer DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROC

3、IRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Charles E. Besore APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, 16-BIT, VOLTAGE OUTPUT DAC, MONOLITHIC SILICON DRAWING APPROVAL DATE 90-04-03 AMSC N/A REVISION LEVEL C SIZE A

4、CAGE CODE 67268 5962-89697 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E501-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89697 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC

5、FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89697 01 X A

6、Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type. The device type identifies the circuit function as follows: Device type Generic number Circuit function 01 AD7846 L2CMOS 16-bit voltage output DAC 1.2.2 Case outlines. The case outlines are as

7、designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Dual-in-line 3 CQCC1-N28 28 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Pos

8、itive supply voltage to DGND (VDD) . -0.3 V dc to +17 V dc Positive logic supply voltage to DGND (VCC) . -0.3 V dc to +7.0 V dc Negative supply voltage to DGND (VSS) +0.3 V dc to -17 V dc VREF+to DGND 25 V dc VREF-to DGND. 25 V dc VOUTto DGND . 25 V dc 1/ RINto DGND 25 V dc Logic input voltage to DG

9、ND . -0.3 V dc to VCC+0.3 V dc Logic output voltage to DGND. -0.3 V dc to VCC+0.3 V dc Storage temperature range . -65C to +150C Lead temperature (soldering, 10 seconds) +300C Power dissipation to 75C (PD) 1000 mW 2/ Thermal resistance, junction to case (JC). See MIL-STD-1835 Junction temperature (T

10、J) +150C 1.4 Recommended operating conditions. Negative supply voltage (VSS) . -14.25 V dc to 15.75 V dc Positive supply voltage (VDD) +14.25 V dc to +15.75 V dc Positive logic supply voltage (VCC) +4.75 V dc to +5.25 V dc Ambient operating temperature range (TA) . -55C to +125C _ 1/ VOUTmay be shor

11、ted to DGND, VDD, VSS, VCCprovided that the power dissipation of the package is not exceeded. 2/ Derate above TA= +75C at 10 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89697 DLA LAND AND MARITIME C

12、OLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the is

13、sues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Stand

14、ard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk,

15、700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulation

16、s unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manu

17、facturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535.

18、 This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accord

19、ance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in acc

20、ordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Output voltage ranges. The output voltage ranges shall be as specified on figure 3. 3.2.5 Logic diagram. The

21、logic diagram shall be as specified on figure 4. 3.2.6 Switching characteristics. The switching characteristics shall be as specified on figure 5. 3.2.7 Load circuits. The load circuits shall be as specified on figure 6. 3.3 Electrical performance characteristics. Unless otherwise specified herein,

22、the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are descri

23、bed in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89697 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteris

24、tics. Test Symbol Conditions 1/ -55C TA+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Resolution RES 1, 2, 3 01 16 Bits Relative accuracy RAUnipolar output 2/ 1, 2, 3 01 -16 +16 LSB Differential nonlinearity 3/ DNL 1, 2, 3 01 -1 +1 Gain error 4/ AE1 01 -16 +16 2,

25、3 -24 +24 Offset error OE1 01 -16 +16 2, 3 -24 +24 Relative accuracy RABipolar output 5/ 1, 2, 3 01 -8 +8 LSB Differential nonlinearity 3/ DNL 1, 2, 3 01 -1 +1 Gain error 4/ AE1 01 -8 +8 2, 3 -16 +16 Offset error 4/ OE1 01 -8 +8 2, 3 -16 +16 Bipolar zero error BIPe1 01 -8 +8 2, 3 -16 +16 Reference i

26、nput resistance RREFINResistance from VREF- to VREF+ 1, 2, 3 01 20 40 k VREF+ range 6/ VREF+ 1, 2, 3 01 VSS+6.0 VDD-6.0 V VREF- range 6/ VREF- 1, 2, 3 01 VSS+6.0 VDD-6.0 V Output swing voltage 6/ VSWING1, 2, 3 01 VSS+4.0 VDD-3.0 V Input voltage high level VIH7, 8 01 2.4 V Input voltage low level VIL

27、7, 8 01 0.8 V Digital input current IIN1, 2, 3 01 10 A Output voltage high level VOHISOURCE= 400 A 1, 2, 3 01 4.0 V Output voltage low level VOLISINK= 1.6 mA 1, 2, 3 01 0.4 V Floating state leakage current ILKGDB0 DB15= 0 V to VCC1, 2, 3 01 10 A Positive power supply current IDDVOUTunloaded 7/ 1, 2,

28、 3 01 5.0 mA Negative power supply current ISS5.0 Positive logic supply current ICC1.0 Power supply sensitivity 8/ PSS 2.0 LSB/V Floating state output capacitance COUTSee 4.3.1c 4 01 10 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without lic

29、ense from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89697 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA+125C unless otherwise specified Group A subg

30、roups Device type Limits Unit Min Max Digital input capacitance CINSee 4.3.1c 4 01 10 pF Functional test See 4.3.1d 7, 8 01 R/ W to CS setup time t1See figure 5 9/ 9 01 40 ns 10, 11 50 CS pulse width (write cycle) t29 01 150 10, 11 190 R/ W to CS hold time t39 01 40 10, 11 50 Data setup time t49 01

31、110 10, 11 120 Data hold time t59, 10, 11 01 0 Data access time 10/ t69 01 230 10, 11 320 Bus relinquish 11/ t79 01 10 80 10, 11 10 90 CLR setup time t89, 10, 11 01 20 CLR pulse width t99, 10, 11 01 150 CLR hold time t109, 10, 11 01 0 LDAC pulse width t119 01 80 10, 11 100 CS pulse width (read cycle

32、) t129 01 240 10, 11 330 1/ Unless otherwise specified, 14.25 V dc VDD 15.75 V dc, -14.25 V dc VSS -15.75 V dc and 4.75 V dc VCC 5.25 V dc. VOUTloaded with 3 k, 1000 pF to 0 V. VREF+ = +5.0 V dc, RIN= connected to 0 V. 2/ VREF- = 0 V, VOUT= 0 V to 10 V, 1 LSB = 153 V. 3/ Monotonicity is guaranteed o

33、ver full temperature range. 4/ VOUTload = 10 M. 5/ VREF= -5.0 V, VOUT= -10 V to +10 V, 1 LSB = 305 V. 6/ If not tested, shall be guaranteed to the limits specified in table I herein. 7/ The device is functional with a power supply of 12 V. 8/ Sensitivity of gain error, offset error and bipolar zero

34、error to VDD, VSSvariations. 9/ All input control signals are specified with tR= tF= 5.0 ns (10% to 90% of +5.0 V) and timed from a voltage level of 1.6 V. 10/ t6is measured with the load circuits for access time on figure 6 and defined as the time required for an output to cross 0.8 V or 2.4 V. 11/

35、 t7is defined as the time required for an output to change 0.5 V when loaded with the circuits for bus relinquish time on figure 6. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89697 DLA LAND AND MARITIME

36、COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 Device type 01 Case outline X and 3 Terminal number Terminal symbol 1 DB2 2 DB1 3 DB0 4 VDD 5 VOUT 6 RIN 7 VREF+ 8 VREF- 9 VSS 10 DB15 11 DB14 12 DB13 13 DB12 14 DB11 15 DB10 16 DB9 17 DB8 18 DB7 19 DB6 20 DGND 21 VCC 22 R/ W 2

37、3 CS 24 CLR 25 LDAC 26 DB5 27 DB4 28 DB3 FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89697 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FOR

38、M 2234 APR 97 CS R/ W LDAC CLR Function 1 X X X 3-state DAC I/O latch in high-Z state 0 0 X X DAC I/O latch loaded with DB15DB0 0 1 X X Contents of DAC I/O latch available on DB15DB0 X X 0 1 Contents of DAC I/O latch transferred to DAC latch X 0 X 0 DAC latch loaded with 000 000 X 1 X 0 DAC latch lo

39、aded with 100 000 0 = Low 1 = High X = Dont care FIGURE 2. Truth table. Output range VREF+ VREF- RIN 0 V to +5.0 V +5.0 V 0 V VOUT 0 V to +10 V +5.0 V 0 V 0 V +5.0 V to -5.0 V +5.0 V -5.0 V VOUT +5.0 V to -5.0 V +5.0 V 0 V +5.0 V +10 V to -10 V +5.0 V -5.0 V 0 V FIGURE 3. Output voltage ranges. Prov

40、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89697 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 FIGURE 4. Logic diagram. Provided by IHSNot for ResaleNo reprod

41、uction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89697 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 FIGURE 5. Switching characteristics. Provided by IHSNot for ResaleNo reproduction or networking p

42、ermitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89697 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 10 DSCC FORM 2234 APR 97 FIGURE 6. Load circuits. (T6) (T7) VOHVOLProvided by IHSNot for ResaleNo reproduction or networking permitted without

43、license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89697 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 11 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein.

44、 In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be

45、 marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compli

46、ance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets t

47、he requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of chan

48、ge to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspe