DLA SMD-5962-89713 REV G-2008 MICROCIRCUIT MEMORY DIGITAL CMOS 4200 GATE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Redrawn with changes. Converted drawing to one part-one part number SMD format. Added package, outline letters U and T. Added devices 03 and 04 93-09-14 M. A. Frye B Added case outline N. Made format changes, editorial changes throughout. 94-02-0

2、4 M. A. Frye C Added case outline M, 9, and 8. Editorial changes throughout. 94-06-06 M. A. Frye D Changes in accordance with NOR 5962-R199-95 95-10-05 M. A. Frye E Changes in accordance with NOR 5962-R003-97 96-10-04 Ray Monnin F Update drawing to current requirements. Editorial changes throughout.

3、 - gap 02-02-01 Ray Monnin G Boilerplate update, part of 5 year review. ksr 08-04-25 Robert M. Heber REV SHET REV G G G G G G G G G G G G G G G G G G G SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 REV STATUS REV G G G G G G G G G G G G G G OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12

4、 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Rajesh Pithadia COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Mike Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWI

5、NG APPROVAL DATE 92-07-28 MICROCIRCUIT, MEMORY, DIGITAL, CMOS 4200 GATE PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON AMSC N/A REVISION LEVEL G SIZE A CAGE CODE 67268 5962-89713 SHEET 1 OF 33 DSCC FORM 2233 APR 97 5962-E347-08 Provided by IHSNot for ResaleNo reproduction or networking permitted witho

6、ut license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89713 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes

7、 Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the f

8、ollowing example: 5962 - 89713 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL

9、-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device ty

10、pe(s) identify the circuit function as follows: Device type Generic number Circuit function Toggle Speed 01 3042-50 12x12 4200 gate programmable array 50 MHz 02 3042-70 12x12 4200 gate programmable array 70 MHz 03 3042-100 12x12 4200 gate programmable array 100 MHz 04 3042-125 12x12 4200 gate progra

11、mmable array 125 MHz 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B micro

12、circuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA15-PN 84 1/ Pin grid array pa

13、ckage Y See figure 1 100 Quad flat package Z CMGA6-PN 132 2/ Pin grid array package U CMGA3-PN 84 1/ Pin grid array package T CQCC1-F100 100 Unformed-lead chip carrier 3/ N See figure 1 100 Quad flat package M See figure 1 100 Quad flat package 9 See figure 1 100 Quad flat package 8 See figure 1 100

14、 Quad flat package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. _ 1/ 84 = actual number of pins used, not maximum listed in MIL-STD-1835. 2/ 132 = actual number of pins used, not maximum listed in MIL-

15、STD-1835. 3/ Pin 1 is the middle pin on the side with center justified identifier mark. Mark may be a notch, dot, or triangle. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89713 DEFENSE SUPPLY CENTER COLUM

16、BUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 3/ Supply voltage range to ground potential (VCC) . -0.5 V dc to +7.0 V dc DC input voltage range -0.5 V dc to VCC+0.5 V dc Voltage applied to three-state output(VTS) . -0.5 V dc to VCC+0.5 V d

17、c Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC): Case outline X, Z, U, and T . See MIL-STD-1835 Case outlines Y, N, M, 9, and 8 . 10C/W 4/ Junction temperature (TJ) +150C 5/ Storage temperature range . -65C to +150C 1.4 Recommended operating conditions. 6/

18、Case operating temperature range(TC) . -55C to +125C Supply voltage relative to ground(VCC) +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) or (VSS) . 0 V dc 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests in accordance with M

19、IL-PRF-38535 95 percent 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the s

20、olicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTME

21、NT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil from the Standardization Document Order Desk, 700 Robin

22、s Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation. ELECTRONICS INDUSTRIES ASSOCIATI

23、ON (EIA) JEDEC Standard EIA/JESD78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizati

24、ons that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 3/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and a

25、ffect reliability. 4/ When a thermal resistance for this case is specified in MIL-STD-1835 that value shall supersede the value indicated herein. 5/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of M

26、IL-STD-883. 6/ All voltage values in this drawing are with respect to VSS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89713 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET

27、 4 DSCC FORM 2234 APR 97 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been

28、 obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect th

29、e form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical

30、 dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shal

31、l be as specified on figure 2. 3.2.3 Logic block diagram. The logic block diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation para

32、meter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The p

33、art shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product us

34、ing this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q

35、and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in

36、 order to supply to the requirements of this drawing (see 6.7.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.7.2 herein). The certificate of compliance submitted to DSCC-VA

37、prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformanc

38、e. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DS

39、CC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers

40、 facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, ap

41、pendix A). 3.11 Operational notes. Additional information shall be provided by the device manufacturer (see 6.6 herein). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89713 DEFENSE SUPPLY CENTER COLUMBUS CO

42、LUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VCC 125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max High level output VOHVCC= 4.5 V, VIL= 0.8 V, 1, 2,

43、3 All 3.7 V voltage IOH= -4.0 mA, VIH= 2.0 V VCC= 4.5 V and 5.5 V, IL= 0.9 V and 1.1 V, VIH= 3.15 V and 3.85 V, IOH= -4.0 mA Low level output VOLVCC= 5.5 V, IOL= 4.0 mA, 1, 2, 3 All 0.4 V voltage VIL= 0.8 V, VIH= 2.0 V VCC= 4.5 V and 5.5 V, IL= 0.9 V and 1.1 V, VIH= 3.15 V and 3.85 V, IOL= 4.0 mA Op

44、erating power supply ICCVCC= 5.5 V 1/ 1, 2, 3 01 245 mA current 02 250 03 260 04 270 Quiescent power supply ICCOCMOS inputs, 1, 2, 3 All 2.0 mA current VCC= VIN= 5.5 V Quiescent power supply ICCOTTL inputs, 1, 2, 3 All 15 mA current VCC= VIN= 5.5 V Power-down supply ICCPDPWRDWN = 0 V, 1, 2, 3 All 1.

45、15 mA current VCC= VIN= 5.5 V Input leakage current IILVCC= 5.5 V, VIN= 0 V and 5.5 V 1, 2, 3 All -20 20 A Output leakage current IOLVCC= 5.5 V, VIN= 0 V and 5.5 V 1, 2, 3 All -20 20 A Horizontal long line, IRLLVCC= 5.5 V, VIN= 0 V and 5.5 V 1, 2, 3 All 2.5 mA pull-up current High level input VIHTTT

46、L inputs 1, 2, 3 All 2.0 V voltage Low level input VILTTTL inputs 1, 2, 3 All 0.8 V voltage High level input VIHCCMOS inputs 1, 2, 3 All 0.7 V voltage VCCLow level input VILCCMOS inputs 1, 2, 3 All 0.2 V voltage VCCPower down ( PWRDWN ) VPD1, 2, 3 All 3.5 V voltage 2/ See footnotes at end of table.

47、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89713 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics -

48、Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Input capacitance except CINSee 4.4.1e 4 All 16 pF XTL1 and XTL2 Input capacitance XTL1 CINSee 4.4.1e 4 All 20 pF and XTL2 Output capacitance COUTSee 4.4.1e 4 All 16 pF Functional test See 4.4.1c 7, 8A, 8B All Interconnect + tPID+ tB1Measured on 12 columns 9, 10, 11 01 192 ns 12(tILO)+ tOP02 122 03 98 04 78 tCKO+ tICK+ tCKI+ tB2Tested on all CLBs 9, 10, 11 01 32