DLA SMD-5962-89724 REV B-2006 MICROCIRCUIT DIGITAL ADVANCED SCHOTTKY OCTAL D FLIP-FLOP WITH THREE-STATE OUTPUTS MONOLITHIC SILICON《硅单片 装有三态输出的八位D型双稳太多谐振荡器 改进型肖特基TTL数字微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R017-92. 91-11-22 Monica L. Poelking B Update to current requirements. Editorial changes throughout. - gap 06-07-06 Raymond Monnin The original first page of this drawing has been replaced. REV SHET REV SHET RE

2、V STATUS REV B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Tim H. Noh DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Tim H. Noh COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY W

3、illiam K. Heckman MICROCIRCUIT, DIGITAL, ADVANCED SCHOTTKY, OCTAL D FLIP-FLOP WITH THREE- AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-08-09 STATE OUTPUTS, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89724 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E3

4、33-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89724 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes d

5、evice requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89724 01 R X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2

6、) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54F574 Octal D flip-flop with three-state outputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Out

7、line letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 dual-in-line S GDFP2-F20 or CDFP3-F20 20 flat 2 CQCC1-N20 20 square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range

8、(VCC) . -0.5 V dc minimum to +7.0 V dc maximum Input voltage range . -0.5 V dc minimum to +7.0 V dc maximum Input current range -30 mA to +5.0 mA Voltage applied to output in the high state -0.5 V dc to VCCCurrent into output in the low state 40 mA Storage temperature range . -65C to +150C Maximum p

9、ower dissipation (PD) 1/ . 495 mW Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) . +4.5 V dc minimum to +5.5 V dc maximum High level input volta

10、ge (VIH) . 2.0 V dc Low level input voltage (VIL) 0.8 V dc Case operating temperature range (TC) -55C to +125C Minimum setup time, Dn to CP (tS) : TC= +25C 2.0 ns TC= -55C, +125C . 2.5 ns _ 1/ Power dissipation is defined as VCCx ICC, and must withstand the added PDdue to short-circuit output test;

11、e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89724 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. -

12、 Continued. Minimum hold time, Dn to CP (th): TC= +25C 1.5 ns TC= -55C, +125C . 2.0 ns Minimum CP pulse width, high (tW(H): TC= +25C 3.0 ns TC= -55C, +125C . 3.0 ns Minimum CP pulse width, low (tW(L): TC= +25C 4.5 ns TC= -55C, +125C . 4.5 ns 2. APPLICABLE DOCUMENTS 2.1 Government specification, stan

13、dards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integ

14、rated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL

15、-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil;quicksearch/ or www.dodssp.daps.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the

16、 event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The in

17、dividual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been gra

18、nted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the

19、 requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. Provided by

20、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89724 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical dimensions. The design,

21、 construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The tr

22、uth table shall be as specified on figure 2. 3.2.4 Test circuit and switching waveforms. The test circuit and switching waveforms shall be specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified

23、 in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance wi

24、th MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-

25、“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify

26、 when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approv

27、ed source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits deli

28、vered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required d

29、ocumentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004

30、of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revisio

31、n level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim

32、 and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MI

33、CROCIRCUIT DRAWING SIZE A 5962-89724 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C Group A subgroups Limits Unit unless otherwise specified Min Max High lev

34、el output voltage VOHVCC= 4.5 V, IOH= -1.0 mA 1, 2, 3 2.5 V VIL= 0.8 V, IH= 2.0 V IOH= -3.0 mA 2.4 Low level output voltage VOLVCC= 4.5 V, VIL= 0.8 V, 1, 2, 3 0.5 V VIH= 2.0 V, IOL= 20 mA Input clamp voltage VICVCC= 4.5 V, IIN= -18 mA 1, 2, 3 -1.2 V High level input current IIH1VCC= 5.5 V, VIN= 2.7

35、V 1, 2, 3 20 A IIH2VCC= 5.5 V, VIN= 7.0 V 1, 2, 3 100 A Low level input current IILVCC= 5.5 V, VIN= 0.5 V 1, 2, 3 -0.6 mA Off-state output current IOZHVCC= 5.5 V, VOUT= 2.7 V 1, 2, 3 50 A IOZLVCC= 5.5 V, VOUT= 0.5 V -50 A Short-circuit output IOSVCC= 5.5 V, VOUT= 0.0 V, 1, 2, 3 -60 -150 mA current S

36、upply current ICCHVCC= 5.5 V 1, 2, 3 65 mA ICCL70 CCZ90 9 110 Maximum clock frequency fMAX 2/ 10, 11 100 MHz Functional tests See 4.3.1c 7, 8 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING

37、 SIZE A 5962-89724 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C Group A subgroups Limits Unit unless otherwise specified Min Max Propagation de

38、lay, tPLHCL= 50 pF, VCC= 5.0 V 9 4.0 8.5 ns CP to Qn RL= 500, VCC= 4.5 V and 5.5 V 10, 11 3.0 9.5 tPHLSee figure 3 VCC= 5.0 V 9 4.0 8.5 CC= 4.5 V and 5.5 V 10, 11 3.0 9.5 Output enable time, tPZHVCC= 5.0 V 9 2.5 8.0 ns OE to high, low VCC= 4.5 V and 5.5 V 10, 11 2.0 9.0 tPZLVCC= 5.0 V 9 3.0 8.5 VCC=

39、 4.5 V and 5.5 V 10, 11 3.0 9.5 Output disable time, tPHZVCC= 5.0 V 9 1.0 6.0 ns OE to high, low VCC= 4.5 V and 5.5 V 10, 11 1.0 7.0 tPLZVCC= 5.0 V 9 1.0 5.5 VCC= 4.5 V and 5.5 V 10, 11 1.0 6.0 1/ Not more than one output will be shorted at one time and the duration of the short-circuit condition sh

40、all not exceed one second. 2/ This parameter is guaranteed but not tested to the limits in table I. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria

41、 shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 4, 5, and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroups 7 and 8 shall include verification of the truth table. 4.3.2 Groups C and D inspections. a. End-point electrical p

42、arameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acqui

43、ring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA= +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-8

44、83. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89724 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Case outlines R, S, and 2 Terminal number Term

45、inal symbols 1 OE 2 D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 GND 11 CP 12 Q7 13 Q6 14 Q5 15 Q4 16 Q3 17 Q2 18 Q1 19 Q0 20 VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-897

46、24 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Inputs Internal Outputs Operating mode OE CP Dn register Q0-Q7 L l L L Load and read register L h H H Load and read register L X NC NC Hold H Dn Dn Z Disable outputs H X X X Z Disable outputs H

47、 = High voltage level h = High voltage level one set-up time prior to the low to high clock transition L = Low voltage level l = Low voltage level one set-up time prior to the low to high clock transition NC = No change X = Irrelevant Z = High impedance “off“ state = Low to high clock transition FIG

48、URE 2. Truth table. Switch position Test Switch tPLZClosed tPZLClosed All others Open FIGURE 3. Test circuit and switching waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89724 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 NOTES: 1. CLincludes