DLA SMD-5962-89754 REV C-2012 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY TTL TRANSCEIVERS REGISTERS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes IAW NOR 5962-R078-93. tvn 93-01-29 Monica L. Poelking B Update to reflect latest changes in format and requirements. Editorial changes throughout. -les 04-08-11 Raymond Monnin C Update drawing as part of 5 year review. jt. 12-09-05 C. SAF

2、FLE THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV SHEET REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Larry T. Gauder DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDA

3、RD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Tim H. Noh APPROVED BY D. M. Cool MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY, TTL, TRANSCEIVERS/REGISTERS, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-12-04 AMSC N

4、/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-89754 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E306-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REV

5、ISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following

6、example: 5962-89754 01 L A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type. The device type identify the circuit function as follows: Device type Generic number Circuit function 01 54F646 Transceivers/registers 02 54F648 Transceivers/register

7、s, inverted 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 dual-in-line K GDFP2-F24 or CDFP3-F24 24 flat 3 CQCC1-N28 28 square chip carrier 1.2.3 Lead finish. The lead

8、finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range . -0.5 V dc to +7.0 V dc Input voltage range . -0.5 V dc to +7.0 V dc Input current range -30 mA to +5.0 mA Voltage applied to any output in the disabled state . -0.5 V dc to +5.5 V dc Voltage app

9、lied to any output in the high state . -0.5 V dc to VCCCurrent into any output in the low state . 96 mA Maximum power dissipation (PD) . 825 mW 1/ Storage temperature range -65C to +150C Ambient temperature under bias . -55C to +125C Lead temperature (soldering, 10 seconds) +300C Junction temperatur

10、e (TJ) +175C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc minimum to +5.5 V dc maximum Minimum high level input voltage (VIH) . 2.0 V dc Maximum low level input voltage (VIL) 0.8 V dc Maximum input clamp curre

11、nt (IIC) . -18 mA Maximum high level output current (IOH) -12 mA Maximum low level output current (IOL) +48 mA Case operating temperature range (TC) -55C to +125C _ 1/ Maximum power dissipation is defined as VCCX ICC, and must withstand the added PDdue to short circuit output test e.g., IO. Provided

12、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions - Continued. Setup time An, Bn

13、, A n, B n to CPAB, CPBA (ts) 5.0 ns Hold time, An, Bn, A n, B n to CPAB, CPBA (th): TC= +25C . 1.5 ns TC= -55C, +125C 2.5 ns Pulse width CPAB, CPBA 5.0 ns Maximum clock frequency (fMAX): TC= +25C . 90 MHz TC= -55C, +125C 75 MHz 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and ha

14、ndbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuit

15、s, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - S

16、tandard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the te

17、xt of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without lic

18、ense from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN c

19、lass level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance

20、 with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the devic

21、e. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall

22、 be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figure 2. 3

23、.2.4 Logic diagrams. The logic diagrams shall be as specified on figure 3. 3.2.5 Test circuit and switching waveforms. Test circuit and switching waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance cha

24、racteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Mark

25、ing shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the opt

26、ion of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance w

27、ith MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land

28、 and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall

29、be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the

30、acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STA

31、NDARD MICROCIRCUIT DRAWING SIZE A 5962-89754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min M

32、ax High level output voltage VOHVCC= 4.5 V, VIL= 0.8 V IOH = -12 mA 1, 2, 3 All 2.0 V Low level output voltage VOLVIH= 2.0 V, IOL= 48 mA 1, 2, 3 All 0.55 V Input clamp voltage VICIC= -18 mA 1, 2, 3 All -1.2 V High level input current IIH1VCC= 5.5 V VIN= 2.7 V (non I/O pins) 1, 2, 3 All 20 A IIH21/ V

33、IN= 7.0 V 100 IIH3VIN= 5.5 V (I/O pins) 1.0 mA Low level input current IILVIN= 0.5 V (non I/O pins) 1, 2, 3 All -0.6 mA Short circuit output current IOS VCC= 5.5 V 2/ VOUT= 0.0 V 1, 2, 3 All -100 -225 mA Off-state output current IOZHVCC= 5.5 V, VIN= 2.7 V 1, 2, 3 01 70 A IOZLVIH= 2.1 V VIN= 0.5 V 01

34、 -650 IOZHVCC= 5.5 V, VIN= 2.7 V 02 70 IOZLVIH= 2.0 V VIN= 0.5 V 02 -650 Supply current ICCHVCC= 5.5 V 1, 2, 3 All 135 mA ICCL150 ICCZ150 Functional tests See 4.3.1c 7, 8 All See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-

35、,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroups Device typ

36、e Limits Unit Min Max Propagation delay time, tPLH1CL= 50 pF VCC= 5.0 V 9 All 1 7 ns An, Bn to Bn, An or A n, R1= 500 VCC = 4.5 V 10, 11 01 1 8 B n to B n, A n R2= 500 to 5.5 V 02 1 9 tPHL1 see figure 4 VCC= 5.0 V 9 All 1 6.5 VCC= 4.5 V to 5.5 V 10, 11 1 8 Propagation delay time, tPLH2VCC= 5.0 V 9 A

37、ll 2 7 ns CPBA, CPAB to An, Bn, VCC= 4.5 V to 5.5 V 10, 11 2 8.5 A n, B n tPHL2VCC= 5.0 V 9 All 2 8 VCC= 4.5 V to 5.5 V 10, 11 2 9.5 Propagation delay time, tPLH3VCC= 5.0 V 9 All 2 8.5 ns SBA, SAB to An, Bn, VCC= 4.5 V to 5.5 V 10, 11 2 11 A n, B n tPHL3VCC= 5.0 V 9 All 2 8 VCC= 4.5 V to 5.5 V 10, 1

38、1 2 10 Output enable time, tPZH1VCC= 5.0 V 9 All 2 8.5 ns OE to An, Bn, A n, B n VCC= 4.5 V to 5.5 V 10, 11 2 10 tPZL1VCC= 5.0 V 9 All 2 8.5 VCC= 4.5 V to 5.5 V 10, 11 2 10 Output enable time, tPZH2VCC= 5.0 V 9 All 2 8.5 ns DIR to An, Bn, A n, B n VCC= 4.5 V to 5.5 V 10, 11 2 10 tPZL2VCC= 5.0 V 9 Al

39、l 2 10 VCC= 4.5 V to 5.5 V 10, 11 2 12 Output disable time, tPHZ1VCC= 5.0 V 9 All 1 7.5 ns OE to An, Bn, A n, B n VCC= 4.5 V to 5.5 V 10, 11 1 9 tPLZ1VCC= 5.0 V 9 All 1 7.5 VCC= 4.5 V to 5.5 V 10, 11 1 9 Output disable time, tPHZ2VCC= 5.0 V 9 All 1 7.5 ns DIR to An, Bn, A n, B n VCC= 4.5 V to 5.5 V

40、10, 11 1 9 tPLZ2VCC= 5.0 V 9 All 1 10 VCC= 4.5 V to 5.5 V 10, 11 1 12 1/ For I/O ports, the parameters IIHand IILinclude the off-state output current. 2 Not more than one output will be shorted at one time and the duration of the short circuit condition shall not exceed one second. Provided by IHSNo

41、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 Device type 01 02 Case outlines K and L 3 K and L 3 Terminal number Terminal

42、 symbol Terminal symbol 1 CPAB NC CPAB NC 2 SAB CPAB SAB CPAB 3 DIR SAB DIR SAB 4 A1DIR A 1 DIR 5 A2A1A 2 A 1 6 A3A2A 3 A 2 7 A4A3A 4 A 3 8 A5NC A 5 NC 9 A6A4A 6 A 4 10 A7A5A 7 A 5 11 A8A6A 8 A 6 12 GND A7GND A 7 13 B8A8B 8 A 8 14 B7GND B 7 GND 15 B6NC B 6 NC 16 B5B8B 5 B 8 17 B4B7B 4 B 7 18 B3B6B 3

43、 B 6 19 B2B5B 2 B 5 20 B1B4B 1 B 4 21 OE B3OE B 3 22 SBA NC SBA NC 23 CPBA B2CPBA B 2 24 VCCB1VCCB 1 25 - - - OE - - - OE 26 - - - SBA - - - SBA 27 - - - CPBA - - - CPBA 28 - - - VCC- - - VCCNC = No connection FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking

44、 permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 Device type 01 Inputs Inputs/Outputs 1/ Operation mode DIR OE CPAB CPBA SAB SBA A0through A7B0through B7X H H/L H/L X

45、 X Input Input Isolation X H X X Input Input Store A and B data L L X X X L Output Input Real time B data to A bus L L X X X H Output Input Stored B data to A bus H L X X L X Input Output Real time A data to B bus H L H/L X H X Input Output Stored A data to B bus Device type 02 Inputs Inputs/Outputs

46、 1/ Operation mode DIR OE CPAB CPBA SAB SBA A 0 through A 7 B 0 through B 7 X H H/L H/L X X Input Input Isolation X H X X Input Input Store A and B data L L X X X L Output Input Real time B data to A bus L L X X X H Output Input Stored B data to A bus H L X X L X Input Output Real time A data to B b

47、us H L H/L X H X Input Output Stored A data to B bus H = High voltage level L = Low voltage level H/L = High or low voltage level X = Irrelevant = Low to high clock transition NOTES: 1. The data output functions may be enabled or disabled by various signals at the OE or DIR inputs. Data input functi

48、ons are always enabled, i.e., data at the bus pins will be stored on every low to high transition of the clock inputs. FIGURE 2. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagrams. Provided by IHSNot for ResaleNo reproduction or networking permitt