DLA SMD-5962-89766 REV B-2010 MICROCIRCUIT DIGITAL FAST CMOS NONINVERTING OCTAL BUFFER LINE DRIVER WITH THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update the boilerplate to current requirements as specified in MIL-PRF-38535. Editorial changes throughout. jak 06-05-01 Thomas M. Hess B Add footnote 5/ for test condition of total power supply current (ICC) to table I. Update boilerplate paragr

2、aphs to the current MIL-PRF-38535 requirements. - LTG 10-01-19 Thomas M. Hess REV SHET REV SHET REV STATUS REV B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Marcia B. Kelleher DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MIC

3、ROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Monica L. Poelking APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, FAST CMOS, NONINVERTING OCTAL BUFFER/LINE DRIVER WITH THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITH

4、IC SILICON DRAWING APPROVAL DATE 89-09-14 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89766 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E139-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89766 DEF

5、ENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Num

6、ber (PIN). The complete PIN is as shown in the following example: 5962-89766 01 R A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 5

7、4FCT541 Noninverting octal buffer/line driver with three-state outputs, TTL compatible inputs 02 54FCT541A Noninverting octal buffer/line driver with three-state outputs, TTL compatible inputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter

8、 Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line S GDFP2-F20 or CDFP3-F20 20 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage

9、range (VCC) . -0.5 V dc to +7.0 V dc Input voltage range (VIN) . -0.5 V dc to VCC + 0.5 V dc Output voltage range (VOUT) -0.5 V dc to VCC+ 0.5 V dc DC input diode current (IIK) . -20 mA DC output diode current (IOK) -50 mA DC output current (IOUT) 100 mA Maximum power dissipation (PD) 2/ 500 mW Stor

10、age temperature range (TSTG) -65C to +150C Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) . +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) . +4.5 V dc to +5.5 V dc Maximum low level input v

11、oltage (VIL). 0.8 V dc Minimum high level input voltage (VIH) . 2.0 V dc Case operating temperature range (TC) -55C to +125C 1/ All voltages are referenced to ground. 2/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permit

12、ted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89766 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standa

13、rds, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

14、 DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of th

15、ese documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited

16、herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix

17、A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML produc

18、t in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or functi

19、on of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical d

20、imensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified o

21、n figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical

22、performance characteristics are as specified in table I and shall apply over the full case operating temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89766 DEFENSE SUPPLY CENTER COLUMBUS COL

23、UMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL

24、-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on t

25、he device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when

26、the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved sou

27、rce of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered

28、to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documen

29、tation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89766 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REV

30、ISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC+125C VCC= 5.0 V dc 10% unless otherwise specified VCCDevice type Group A subgroups Limits Unit Min Max High level output voltage VOHVIL= 0.8 V VIH= 2.0 V IOH= -300 A 4.5 V A

31、ll 1, 2, 3 4.3 V IOH= -12 mA 4.5 V 2.4 Low level output voltage VOLVIL= 0.8 V VIH= 2.0 V IOL= +300 A 4.5 V All 1, 2, 3 0.2 V IOL= +48 mA 4.5 V 0.55 Input clamp voltage VIKIIN= -18 mA 4.5 V All 1, 2, 3 -1.2 V High level input current IIHVIN= 5.5 V 5.5 V All 1, 2, 3 5.0 A Low level input current IILVI

32、N= GND 5.5 V All 1, 2, 3 -5.0 A High impedance output current IOZHVIN= 5.5 V 5.5 V All 1, 2, 3 10.0 A IOZLVIN= GND 5.5 V All 1, 2, 3 -10.0 A Short circuit output current IOS1/ VOUT= GND 5.5 V All 1, 2, 3 -60 mA Quiescent power supply current (CMOS inputs) ICCQVIN 0.2 V or VIN 5.3 V fin= 0 MHz 5.5 V

33、All 1, 2, 3 1.5 mA Quiescent power supply current (TTL inputs) ICC2/ VIN= 3.4 V 5.5 V All 1, 2, 3 2.0 mA Dynamic power supply current ICCDOEA = OEB = GND One bit toggling, 50% duty cycle VIN 0.2 V or VIN 5.3 V Outputs open 5.5 V All 3/ 0.4 mA/ MHz Total power supply current ICC4/ 5/ VIN 0.2 V or VIN

34、 5.3 V OEA = OEB = GND One bit toggling, 50% duty cycle Outputs open, fi= 10 MHz 5.5 V All 1, 2, 3 5.5 mA VIN= GND or VIN= 3.4 V OEA = OEB = GND One bit toggling, 50% duty cycle Outputs open, fi= 10 MHz 5.5 V All 1, 2, 3 6.0 mA Input capacitance CINSee 4.3.1c All 4 10 pF Output capacitance COUTSee 4

35、.3.1c All 4 12 pF Functional tests See 4.3.1d 4.5 V All 7, 8 Propagation delay time, Dn to On tPHL, tPLH6/ CL= 50 pF RL= 500 See figure 4 4.5 V 01 9, 10, 11 2.0 9.0 ns 02 2.0 5.1Propagation delay time, output enable, OEA or OEB to On tPZH, tPZL6/ 4.5 V 01 9, 10, 11 2.0 12.5 ns 02 2.0 6.5Propagation

36、delay time, output disable, OEA or OEB to On tPHZ, tPLZ6/ 4.5 V 01 9, 10, 11 2.0 12.5 ns 02 2.0 5.9See footnotes on next sheet. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89766 DEFENSE SUPPLY CENTER COLU

37、MBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. 1/ Not more than one output should be shorted at one time, and the duration of the short circuit condition should not exceed one second. 2/ TTL driven input (VIN=

38、3.4 V); all other inputs at VCCor GND. 3/ This parameter is not directly testable, but is derived for use in total power supply calculations. 4/ ICC= ICCQ+ (ICCx DHx NT) + (ICCDx fIx NI) Where: DH= Duty cycle for TTL inputs high. NT= Number of TTL inputs at DH.fI= Input frequency in MHz. NI= Number

39、of inputs at fI. 5/ For ICCtest in an ATE environment, the effect of parasitic output capacitive loading from the test environment must be taken into account, as its effect is not intended to be included in the test results. The impact must be characterized and appropriate offset factors must be app

40、lied to the test result. 6/ The minimum limits are guaranteed, if not tested, to the specified limits. Device types 01 and 02 Case outlines R, S, and 2 Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OEA D0 D1 D2 D3 D4 D5 D6 D7 GND O7 O6 O5 O4 O3 O2 O1 O0 OEB VCCFI

41、GURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89766 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Device types 01 and

42、02 Inputs Outputs OEA OEB Dn On L L L L L L H H H X X Z X H X Z L = Low voltage level H = High voltage level X = Dont care Z = High impedance FIGURE 2. Truth table. FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MIC

43、ROCIRCUIT DRAWING SIZE A 5962-89766 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 NOTES: 1. When measuring tPLH, tPHLtPZHand tPHZ: S1 = Open. When measuring tPLZand tPZL: S1 = Closed. 2. RL= 500 or equivalent. 3. RT= 50 or equivalent, termina

44、l resistance which should be equal to ZOUTof the pulse generator. 4. CL= 50 pF or equivalent (includes test jig and probe capacitance). 5. Diagram shown for input control enable-low and input control disable-high. 6. Pulse generator for all pulses: tr 2.5 ns; tf 2.5 ns. FIGURE 4. Switching waveforms

45、 and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89766 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling an

46、d inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria sh

47、all apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the

48、 inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters (met