DLA SMD-5962-89815 REV B-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 2K X 8 REGISTERED UVEPROM MONOLITHIC SILICON《硅单片 2K X 8寄存的紫外线消除式可程序化只读存储器 氧化物半导体数字记忆微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. Removed programming specifics from drawing. Editorial changes throughout. gap 01-02-07 Raymond Monnin B Boilerplate update and part of five year review. tcr 07-02-13 Joseph Rodenbeck THE ORIGINAL F

2、IRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV SHET REV STATUS REV B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY James E. Jamison DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/ww

3、w.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 8 REGISTERED UVEPROM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 91-12-30 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268

4、 5962-89815 SHEET 1 OF 11 DSCC FORM 2233 APR 97 5962-E261-07 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89815 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2

5、234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89815 01 K X Drawin

6、g number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Setup time 01 7C245A-35 2K x 8 registered UV EPROM 35 ns 02 7C245A-25 2K x 8 registered UV EPR

7、OM 25 ns 03 7C245A-18 2K x 8 registered UV EPROM 18 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 flat package 1/ L GDIP3-T24 or CDIP4-T24 24 dual-in-line packa

8、ge 1/ 3 CQCC1-N28 28 square leadless chip carrier package 1/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC voltage applied to outputs in high Z state -0.5 V dc to +7.0 V dc DC input

9、voltage . -3.0 V dc to +7.0 V dc DC program voltage 13.0 V dc Maximum power dissipation 2/ . 1.0 W Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C Storage temperature range . -65C to +150C Temperature under b

10、ias -55C to +125C Endurance . 10 cycles/byte, minimum Data retention 10 years, minimum 1.4 Recommended operating conditions. Supply voltage range (VCC) . +4.5 V dc to +5.5 V dc Ground voltage (GND) . 0 V dc Input high voltage (VIH) . 2.0 V dc minimum Input low voltage (VIL) 0.8 V dc maximum Case ope

11、rating temperature range (TC) -55C to +125C _ 1/ Lid shall be transparent to permit ultraviolet light erasure. 2/ Must withstand the added PDdue to short circuit test (e.g., IOS). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT

12、DRAWING SIZE A 5962-89815 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the e

13、xtent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Met

14、hod Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps

15、.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this dr

16、awing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B

17、 devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the ma

18、nufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These mod

19、ifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as speci

20、fied in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. Provided by IHS

21、Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89815 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.2.3.1 Unprogrammed or erased devices. The truth table for unpro

22、grammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in screening (see 4.2) group A, C, or D (see 4.3), the devices shall be programmed by the manufacturer prior to test with a checkerboard pattern or equivalent (a minimum of 50 percent of

23、the total number of bits programmed) or to any altered item drawing pattern which includes at least 25 percent of the total number of bits programmed. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.3 Electrical performa

24、nce characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table

25、II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire

26、 SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance

27、indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply

28、 in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certif

29、icate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs

30、 agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Processing EPROMS. All testing requirements and quality assurance provisions her

31、ein, shall be satisfied by the manufacturer prior to delivery. 3.10.1 Erasure of EPROMS. When specified, devices shall be erased in accordance with the procedures and characteristics specified by the manufacturer. 3.10.2 Programmability of EPROMS. When specified, devices shall be programmed to the s

32、pecified pattern using the procedures and characteristics specified by the manufacturer. 3.10.3 Verification of programmed or erased EPROMs. When specified, devices shall be verified as either programmed to a specified program, or erased. As a minimum, verification shall consist of performing a func

33、tional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.11 Data retention. A data retention stress test shall be completed as part of the vendors reliabili

34、ty monitors. This test shall be done for initial characterization and after any design or process change which may affect data retention. The methods and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military temperature range.

35、The vendors procedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with test data. 3.12 Endurance. A reprogrammability test shall be completed as part of the vendors reliability monitors. This test shall be done for initi

36、al characterization and after any design or process change which may affect the reprogrammability of the device. The methods and procedures may be vendor specific, but shall guarantee the number of program/erase endurance cycles listed in section 1.3 herein over the full military temperature range.

37、The vendors procedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with test data.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962

38、-89815 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/, 2/ -55C TC+125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Outp

39、ut high voltage VOHVCC= 4.5 V, IOH= -4.0 mA 1, 2, 3 All 2.4 V VIN= VIH, VILOutput low voltage VOLVCC= 4.5 V, IOL= 16.0 mA 1, 2, 3 All 0.4 V IN= VIH, VILInput high voltage 1/ VIH1, 2, 3 All 2.0 V Input low voltage 1/ VIL1, 2, 3 All 0.8 V Input leakage current IIXVIN= VCCto GND 1, 2, 3 All -10 +10 A O

40、utput leakage current IOZVOUT= VCCto GND 1, 2, 3 All -40 +40 A 3/ Output short circuit IOSVCC= 4.5 V, and 5.5 V 1, 2, 3 All -20 -90 mA current 4/, 5/ VOUT= 0.0 V Power supply current ICCE / ES= VIL, INIT = VIH, 1, 2, 3 All 120 mA Addresses cycling between 0 V and 3 V, VCC= 5.5 V, f = PWCt21Input cap

41、acitance 5/ CINVCC= 5.0 V, VIN= 0 V 4 All 10 pF TA= +25C, f = 1 MHz (see 4.3.1c) Output capacitance 5/ COUTVCC= 5.0 V, VOUT= 0 V 4 All 10 pF TA= +25C, f = 1 MHz (see 4.3.1c) Functional tests See 4.3.1e 7, 8 All Address setup to clock tSASee figures 3 and 4 6/ 9, 10, 11 01 35 ns high 02 25 03 18 Addr

42、ess hold from clock tHA9, 10, 11 All 0 ns high Clock high to valid tCO9, 10, 11 01 15 ns output 02, 03 12 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89815 DEFENSE SUPPLY CE

43、NTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/, 2/ -55C TC+125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Clock pulse widt

44、h 5/ tPWCSee figures 3 and 4 6/ 9, 10, 11 01 20 ns 02 15 03 12 ESsetup to clock tSES9, 10, 11 01 15 ns high 5/ 02 12 03 10 EShold from clock tHES9, 10, 11 All 5 ns high 5/ Delay from INIT to tDI9, 10, 11 All 20 ns valid output INIT recovery to clock tRI9, 10, 11 01 20 ns high 02, 03 15 INIT pulse wi

45、dth tPWI9, 10, 11 01 20 ns 02, 03 15 Valid output from clock tCOS9, 10, 11 01 20 ns high 5/, 7/ 02, 03 15 Inactive output from tHZC9, 10, 11 01 20 ns clock high 5/, 7/, 8/ 02, 03 15 Valid output from E low tDOE9, 10, 11 01 20 ns 9/ 02, 03 15 Inactive output from tHZE9, 10, 11 01 20 ns E high 5/, 8/,

46、 9/ 02, 03 15 1/ These are absolute voltages with respect to device ground pin and include all overshoots due to system or tester noise. 2/ AC tests are performed with input rise and fall times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and the output load o

47、n figure 3. 3/ For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement. 4/ For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 5/ This parameter teste

48、d initially and after any design or process changes which could affect this parameter, and therefore shall be guaranteed to the limits specified in table I. 6/ See figure 3, circuit A, for all switching characteristics except tHZ. 7/ Applies only when the synchronous ( ES) function is used. 8/ Transition is measured at steady-state high level -500 mV or steady-state low level +500 mV on the output from the 1.5 V level on the input with the output load on figure 3, circuit B. 9/ Applies only when the asynchrono