DLA SMD-5962-89830 REV D-2007 MICROCIRCUIT LINEAR DATA ACQUISITION SYSTEM MONOLITHIC SILICON《硅单片 资料收集系统 线性微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R119-92. 92-02-12 M. A. Frye B Add device types 02, 03, and 04. Changes in table I and figure 1. Editorial changes throughout. 93-05-26 M. A. Frye C Changes in accordance with NOR 5962-R010-94. 93-10-15 M. A. F

2、rye D Incorporate revision C, NOR. Update drawing to current requirements. Editorial changes throughout. - drw 07-04-25 Robert M. Heber THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV SHET REV STATUS REV D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A

3、PREPARED BY Rick C. Officer DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles E. Besore COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, DATA ACQUISITION AND AGENCIES

4、OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 90-03-08 SYSTEM, MONOLITHIC SILICON AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-89830 SHEET 1 OF 11 DSCC FORM 2233 APR 97 5962-E386-07 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDA

5、RD MICROCIRCUIT DRAWING SIZE A 5962-89830 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-3

6、8535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89830 01 R A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device types. The device types identify the circuit function as follows: Device

7、type Generic number Circuit function Gain error 01 LTC1090 10-bit data acquisition system 2.0 LSB 02 LTC1290B 12-bit data acquisition system 0.5 LSB 03 LTC1290C 12-bit data acquisition system 1.0 LSB 04 LTC1290D 12-bit data acquisition system 4.0 LSB 1.2.2 Case outline. The case outline is as design

8、ated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage (V+) to GND or (V-) . 12 Vdc Negati

9、ve supply voltage (V-) -6 V to GND Analog and reference input voltage range . (V-) -0.3 V to V+ +0.3 V Digital input voltage range . -0.3 V to 12 V Digital output voltage range . -0.3 V to V+ +0.3 V Power dissipation (PD) . 500 mW Lead temperature (soldering, 10 seconds) +300C Storage temperature ra

10、nge -65C to +150C Junction temperature (TJ) +175C Thermal resistance, junction-to-case (JC). See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA) 70C/W _ 1/ All voltage values are with respect to ground with DGND, AGND, and REF- wired together, unless otherwise noted. Provided by IHSNot for

11、 ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89830 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. 2/ Positive supply voltage range (

12、V+) 4.5 V dc to 10 V dc Negative supply voltage range (V-) -5.5 V dc to 0 V dc Shift clock frequency range (fSCLK): Device type 01 . 0 to 1.0 MHz Device type 02, 03, 04 0 to 2.0 MHz A/D clock frequency range (fACLK): Device type 01 . fSCLKto 2.0 MHz Device type 02, 03, 04 fSCLKto 4.0 MHz Total cycle

13、 time (tCYC): Device type 01 . 10 SCLK + 48 ACLK cycles minimum Device type 02, 03, 04 12 SCLK + 56 ACLK cycles minimum Hold time, CS low after last SCLK negative edge (tHCS) . 0 ns minimum Hold time, DINafter SCLK positive edge (tHD): Device type 01 . 150 ns minimum Device type 02, 03, 04 50 ns min

14、imum Setup time, CS negative edge before clocking in first address bit (tSUCS): Device type 01 . 2 ACLK cycles + 1 s minimum Device type 02, 03, 04 2 ACLK cycles + 100 ns minimum Setup time, DINstable before SCLK positive edge (tSUD): Device type 01 . 400 ns minimum Device type 02, 03, 04 50 ns mini

15、mum ACLK high time (tWHACLK), device type 01 127 ns minimum ACLK low time (tWLACLK), device type 01 200 ns minimum CS high time during conversion (tWHCS): Device type 01 . 44 ACLK cycles ninimum Device type 02, 03, 04 52 ACLK cycles ninimum Ambient operating temperature range (TA) -55C to +125C 2. A

16、PPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEP

17、ARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-

18、HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, P

19、hiladelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has

20、been obtained. _ 2/ V+ = 5.0 V dc, unless otherwise noted. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89830 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 223

21、4 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qua

22、lified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Qual

23、ity Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to i

24、dentify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal

25、connections. The terminal connections shall be as specified on figure 1. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electr

26、ical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 here

27、in. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall

28、 be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of com

29、pliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements

30、 of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA s

31、hall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of

32、the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89830 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance char

33、acteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxHigh level input voltage VIHV+ = 5.25 V 1, 2, 3 All 2.0 V Low level input voltage VILV+ = 4.75 V 1, 2, 3 All 0.8 V High level input current IIHVIN= V+ 1, 2, 3 All 2.5 A Lo

34、w level input current IILVIN= 0 V 1, 2, 3 All -2.5 A High level output voltage VOHV+ = 4.75 V, IO= 360 A 1, 2, 3 All 2.4 V Low level output voltage VOLV+ = 4.75 V, IO= 1.6 mA 1, 2, 3 All 0.4 V Hi-Z output leakage IOZVOUT= V+, CS high 1, 2, 3 All 3.0 A VOUT= 0 V, CS high -3.0 Positive supply current

35、I+ CS high, REF+ open 1, 2, 3 01 2.5 mA 02, 03, 04 12 Reference current IREFVREF= 5 V 1, 2, 3 01 1.0 mA 02, 03, 04 0.05 Negative supply current I- CS high, V- = -5 V 1, 2, 3 All 50 A Offset error 2/ VOS1, 2, 3 01 0.5 LSB 02, 03, 04 1.5 Linearity error 2/, 3/ 1, 2, 3 01, 02, 03 0.5 LSB 04 0.75 Gain e

36、rror 2/ AE1, 2, 3 01 2.0 LSB 02 0.503 1.004 4.0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89830 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D S

37、HEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxTotal unadjusted error 2/, 4/ VREF= 5 V 1, 2, 3 01 2.0 LSB Analog and REF input range 5/ 1, 2, 3

38、 All (V-) -0.02 (V+) +0.02 V On channel leakage current 6/ RONOn channel = 5 V, Off channel = 0 V 1, 2, 3 All 1 A On channel = 0 V, Off channel = 5 V -1 Off channel leakage current 6/ ROFFOn channel = 5 V, Off channel = 0 V 1, 2, 3 All 1 A On channel = 0 V, Off channel = 5 V -1 Delay time, SCLK nega

39、tive edge to DOUTdata valid tdDOSee figures 2 and 3 9, 10, 11 01 450 ns 02, 03, 04 270 Delay time, CS positive edge to DOUTHi-Z tdisSee figures 2 and 3 9, 10, 11 01 300 ns 02, 03, 04 100 Delay time, 2nd CLK negative edge to DOUTtenSee figures 2 and 3 9, 10, 11 01 400 ns enabled 02, 03, 04 200 DOUTfa

40、ll time tfSee figures 2 and 3 9, 10, 11 01 300 ns 02, 03, 04 130 DOUTrise time trSee figures 2 and 3 9, 10, 11 01 300 ns 02, 03, 04 50 1/ V+ = 5 V, VREF+= 5 V, VREF-= 0 V, V- = 0 V for unipolar mode and -5 V for bipolar mode, ACLK = 4.0 MHz unless otherwise specified. 2/ Applies for both unipolar an

41、d bipolar modes. 3/ Linearity error is specified between the actual end-points of the A/D transfer curve. 4/ Total unadjusted error includes offset, gain, linearity, multiplexer and hold step errors. 5/ Two on-chip diodes are tied to each reference and analog input which will conduct for reference o

42、r analog input voltages, one diode drop below V- or one diode drop above VCC. Be careful during testing at low VCClevels (4.5 V), as high level reference or analog inputs (5 V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for inputs near full-scale. Th

43、is specification allows 50 mV forward bias of either diode. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 V to 5 V input voltage range will therefore require a minimum supply v

44、oltage of 4.950 V over initial tolerance, temperature variations and loading. 6/ Channel leakage current is measured after the channel selection Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89830 DEFENSE S

45、UPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 Device type 01, 02, 03, 04 Case outline R Terminal number Terminal symbol 1 CH0 2 CH1 3 CH2 4 CH3 5 CH4 6 CH5 7 CH6 8 CH7 9 COM 10 DGND 11 AGND 12 V- 13 REF- 14 REF+15 CS 16 DOUT17 DIN18 SCLK 19 ACLK 20 V+

46、 FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89830 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 NOTES: 1. Wavefor

47、m 1 is for an output with internal conditions such that the output is high unless disabled by the output control. 2. Waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. FIGURE 2. Timing waveforms. Provided by IHSNot for ResaleNo rep

48、roduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89830 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 FIGURE 3. Test circuits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89830 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 1