DLA SMD-5962-89841 REV L-2008 MICROCIRCUIT MEMORY DIGITAL CMOS PROGRAMMABLE ARRAY LOGIC (EEPLD) MONOLITHIC SILICON《微电路记忆数字式CMOS可编程阵列逻辑(EEPLD)》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added K package. Added 04 device, two suppliers and 05 device, one supplier. Added vendor CAGE 34335 for devices 01L, 013, and 02L. Editorial changes throughout. Added vendor CAGE 34335 for devices 01K, 023, and 02K. Redrawn. 91 04 19 M. A. Frye

2、B Added vendor CAGE 65786 for devices 01, 02, 03, 04, and 05LX, KX, and 3X. Added vendor CAGE 18324 for devices 01, 02, 04, and 05LX. IAW NOR 5962-R079-93. 93 01 28 M. A. Frye C Added 06 device for one supplier. Added test tSU2to table I. Editorial changes throughout. Redrawn. 93 07 30 M. A. Frye D

3、Added devices 07-14, Added CAGE 1FN41 for devices 13 and 14, added test ICCSBto table I for devices 13 and 14, and updated text to newer boiler plate. 97 03 04 Raymond Monnin E Changes in accordance with NOR 5962-R263-97 97 04 23 Raymond Monnin F Changes in accordance with NOR 5962-R341-97 97 06 05

4、Raymond Monnin G Added powerup-reset parameters to table I, and the waveform as figure 5. Updated boilerplate. ksr 98 07 10 Raymond Monnin H Changed minimum IOS value for devices 01 thru 06 on table I. Value was changed from -50 mA to -30 mA. ksr 99 03 19 Raymond Monnin J Updated boiler plate. ksr 0

5、2 - 10 - 10 Raymond Monnin K Boilerplate update, part of 5 year review. ksr 08 06 - 04 Robert M. Heber L Added devices 15 and 16. Updated Table I, added Figure 6 for devices 15 and 16. ksr 08 -08-25 Robert M. Heber REV SHEET REV L L L L L SHEET 15 16 17 18 19 REV STATUS REV L L L L L L L L L L L L L

6、 L OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. F

7、rye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89 11 28 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, PROGRAMMABLE ARRAY LOGIC (EEPLD), MONOLITHIC SILICON SIZE A CAGE CODE 67268 5962-89841 AMSC N/A REVISION LEVEL L SHEET 1 OF 19 DSCC FORM 2233 APR 97 5962-E482-08 Provided by IHSNot for R

8、esaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89841 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL L SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD

9、-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89841 01 K A Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2

10、.1 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit function Access time 01, 07 22V10 22-input, 10-output, EECMOS, architecturally 30 generic, programmable AND-OR array 02, 08 22V10 22-input, 10-output, EECMOS, architecturally 20 g

11、eneric, programmable AND-OR array 03, 09, 15 22V10 22-input, 10-output, EECMOS, architecturally 15 generic, programmable AND-OR array 04, 10 22V10 22-input, 10-output, EECMOS, architecturally 25 generic, programmable AND-OR array 05, 11 22V10 22-input, 10-output, EECMOS, architecturally 15 generic,

12、programmable AND-OR array (higher tCO, lower fCLK2) 06, 12, 16 22V10 22-input, 10-output, EECMOS, architecturally 10 generic, programmable AND-OR array 13 22V10L 22-input, 10-output, EECMOS, architecturally 25 generic, programmable AND-OR array 14 22V10L 22-input, 10-output, EECMOS, architecturally

13、20 generic, programmable AND-OR array 1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 flat pack L GDIP3-T24 or CDIP4-T24 24 dual-in-line 3 CQCC1-N28 28 square c

14、hip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range - -0.5 V dc to +7.0 V dc Input voltage applied - -0.5 V dc to VCC+1.0 V dc 1/ Off-state output voltage applied - -0.5 V dc to VCC+1.0 V dc 1/ Storage temper

15、ature range (TSTG) - -65C to +150C Maximum power dissipation (PD) 2/ - 1.5 W Lead temperature (soldering, 10 seconds) (TSOL) - +260C Thermal resistance, junction-to-case (JC) - See MIL-STD-1835 Junction temperature (TJ)- +175C Data retention- 10 years (minimum) Endurance - 100 erase/write cycles (mi

16、nimum) _ 1/ Minimum voltage is -0.5 V which may undershoot to -2.5 V for pulses of less than 20 ns. 2/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE

17、 A 5962-89841 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL L SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage range (VCC)- 4.5 V dc to 5.5 V dc High level input voltage (VIH)- 2.0 V dc to VCC+1.0 V dc Low level input voltage (VIL) - VSS-0.

18、5 V dc to +0.8 V dc High level output current (IOH) - -2.0 mA maximum Low level output current (IOL) - 12 mA maximum Case operating temperature range (TC) - -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handb

19、ooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF

20、 DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents

21、are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the tex

22、t of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN c

23、lass level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance

24、 with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the devic

25、e. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall

26、 be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1. Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Truth table. The truth table shall be as specified on figure 2. 3.2.2.1 Unprogrammed devices. The truth table for unprogrammed devices shall be as

27、specified on figure 2. 3.2.2.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.2.3 Case outlines The case outlines shall be in accordance with 1.2.2 herein. Provided by IHSNot for ResaleNo reproduction or networking permitted wi

28、thout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89841 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL L SHEET 4 DSCC FORM 2234 APR 97 Table I. Electrical performance characteristics. Test Symbol Conditions Group A Device Limits Unit -55C TC +125C subgroup

29、s type VSS= 0 V, 4.5 V VCC 5.5 V unless otherwise specified Min Max Input leakage current 1/ ILX0.0 V VIN VCC1, 2, 3 01-06, 13,14 10 -150 A 7-12 -10 10 2/ 15, 16 -10 Bidirectional pin leakage current 1/ II/O/Q0.0 V VI/O/Q VCC1, 2, 3 01-06, 13,14 10 -150 A 7-12 -40 40 2/ 15, 16 -10 10 Output low volt

30、age VOLVCC= 4.5 V, IOL= 12 mA, 1, 2, 3 All 0.5 V VIN= VIHor VILOutput high voltage VOHVCC= 4.5 V, IOH= -2 mA, 1, 2, 3 All 2.4 V IN= VIHor VILInput low voltage 3/ VIL1, 2, 3 All 0.8 V Input high voltage 3/ VIH1, 2, 3 All 2.0 V Operating power supply current ICCVIL= 0.5 V, VIH= 3.0 V 1, 2, 3 01-06 150

31、 mA f tog= 15 MHz 07-12 130 13,14 70 VIL= 0.0 V, VIH= VCCf tog= 15 MHz 15,16 160 Power supply ICCSBVIN0 V or VCC1, 2, 3 mA current standby f tog= 0 MHz 13,14 15 Output short circuit current 4/ IOSVCC= 5.0 V, VOUT= 0.5 V 1, 2, 3 01-06 -30 -135 TA= 25C see 4.3.1d 07-12 -30 -90 mA Input capacitance CIN

32、VCC= 5.0 V, VI= 2.0 V 4 All 10 pF f = 1.0 MHz, TA= +25C, See 4.3.1c Bidirectioanl pin capacitance CI/O/QVCC= 5.0 V, VI/O/Q= 2.0 V 4 All 10 pF f = 1.0 MHz, TA= +25C, See 4.3.1c Functional tests See 4.3.1e 7, 8A,8B All See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or netw

33、orking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89841 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL L SHEET 5 DSCC FORM 2234 APR 97 Table I. Electrical performance characteristics - Continued. Test Symbol Conditions Group A Device Lim

34、its Unit -55C TC +125C subgroups type VSS= 0 V, 4.5 V VCC 5.5 V unless otherwise specified Min Max Input or feedback to nonregistered output tPDVCC= 4.5 V, see figures 3 and 4 5/ 9, 10, 11 01 30 ns 02 20 03, 05, 15 15 08, 09, 11 3 15 04 25 06, 16 10 12 3 10 07,10, 13 3 25 14 3 20 Clock to output del

35、ay 6/ tCO9, 10, 11 01,04 20 ns 02 15 07, 10, 14 2 15 03, 15 8 08, 09, 11 2 8 05 12 06, 16 7 12 2 13 20 Input to output enable tEA9, 10, 11 01,04,07,10,13 25 ns 02, 14 20 03, 05, 08,09,11, 15 15 06, 12, 16 10 Input to output disable 7/ tER9, 10, 11 01,04, 07,10, 13, 25 ns 02, 14 20 03, 05, 08,09,11,1

36、5 15 06, 16 12 12 10 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89841 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL L SHEET 6 DSCC FORM 2234 APR 9

37、7 Table I. Electrical performance characteristics Continued. Test Symbol Conditions Group A Device Limits Unit -55C TC +125C subgroups type VSS= 0 V, 4.5 V VCC 5.5 V unless otherwise specified Min Max Asynchronous register reset 6/ tRESVCC= 4.5 V, see figures 3 and 4 5/ 9, 10, 11 01,04,13 30 ns 02,0

38、7,10,14 25 03,05, 08,09,11, 15 20 06,12, 16 12 Clock frequency without fCLK19, 10, 11 01 0 25.0 MHz feedback 6/ 8/ 02,14, 0 33.3 1/(tPWH+ tPWL) 07,10 0 35.7 03, 05 62.5 08, 09, 11 0 83.3 04, 13 0 33.0 15 0 100.0 12 0 142.0 16 0 143.0 06 0 166.0 Clock frequency with fCLK29, 10, 11 01 0.0 22.0 MHz fee

39、dback 6/ 8/ 07,10 0.0 30.3 1/(tCO+ tSU1) 02,14 0.0 31.2 03,08,09,11 0.0 50.0 04, 13 0.0 26.3 05 0.0 42.0 15 0.0 62.5 16 0.0 83.3 06,12 0.0 76.9 Input or feedback setup tSU19, 10, 11 01 25 ns time before rising clock 02, 14 17 6/ 03,05 12 08, 09, 10 11 04, 07, 18 10, 13 15 8 06, 12 6 16 5 See footnot

40、es at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89841 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL L SHEET 7 DSCC FORM 2234 APR 97 Table I. Electrical performanc

41、e characteristics - Continued. Test Symbol Conditions Group A Device Limits Unit -55C TC +125C subgroups type VSS= 0 V, 4.5 V VCC 5.5 V unless otherwise specified Min Max Synchronous Preset setup time tSU2VCC= 4.5 V, see figures 3 and 4 5/ 9, 10, 11 01 25 ns 02, 14 17 08, 09, 11 10 03, 05, 15 12 04,

42、 07, 10, 13 18 06, 12, 16 7 Input or feedback hold time after rising th9, 10, 11 All 0 ns clock 6/ Clock pulse width, high tPWH9, 10, 11 01 20 ns 6/ 02, 14 15 03, 05 8 04, 13 15 07, 10 14 08, 09, 11 6 15 5 06, 12 7/ 3 16 3.5 Clock pulse width, low tPWL9, 10, 11 01 20 ns 6/ 02, 14 15 03, 05 8 04, 13

43、15 07, 10 14 08, 09, 11 6 15 5 06, 12 7/ 3 16 3.5 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89841 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL L SHEET 8 DSCC FORM 2234 APR 97

44、Table I. Electrical performance characteristics - Continued. Test Symbol Conditions Group A Device Limits Unit -55C TC +125C subgroups type VSS= 0 V, 4.5 V VCC 5.5 V unless otherwise specified Min Max Asynchronous reset pulse width tPWRVCC= 4.5 V, see figures 3 and 4 5/ 9, 10, 11 01 30 ns 02, 14 20

45、03, 05, 08, 09, 11, 15 15 04, 07, 10, 13 25 06, 12, 16 10 Asynchronous reset to rising clock recovery time tREC9, 10, 11 01 30 ns 02, 14 20 03, 05 15 08, 09, 11, 15 12 04, 07, 10, 13 25 06, 12, 16 6 Clock pulse width tWSee figure 5 9, 10, 11 01, 07 20 ns 6/ 8/ 04, 10, 13 15 02, 08, 14 15 03, 05, 09, 11, 15 8 06, 12, 16 3.5 Setup time tS9, 10, 11 01, 07 25 ns 6/ 8/ 04, 10, 13 18 02, 08, 14 17 03, 05, 09, 11, 15 12 06, 12, 16 6 Power up reset time 8/ tPR9, 10, 11 All 1.0 s See f