DLA SMD-5962-89928 REV B-2007 MICROCIRCUIT LINEAR TRIPLE 8-BIT D A CONVERTER WITH A 256 X 24 COLOR PALETTE MONOLITHIC SILICON《硅单片 装有256 X 24调色板三重8位直流 交流转变器 线性微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R197-93. 93-07-20 M. A. Frye B Incorporate revision A, NOR. Update drawing to current requirements. Editorial changes throughout. drw 07-07-02 Robert Heber THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPL

2、ACED. REV SHET REV B B SHET 15 16 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rick C. Officer DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles E. Besore COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mi

3、l THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, TRIPLE 8-BIT, D/A CONVERTER WITH A 256 X 24 COLOR PALETTE, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 90-07-23 MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 6

4、7268 5962-89928 SHEET 1 OF 16 DSCC FORM 2233 APR 97 5962-E459-07 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89928 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FO

5、RM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89928 01 X A Dr

6、awing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type. The device type identifies the circuit function as follows: Device type Generic number Circuit function 01 Bt458 Triple, 8-bit D/A converter with a 256 X 24 color palette and binary output coding 1.

7、2.2 Case outline. The case outline is as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA16-PN 84 Pin grid array 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltag

8、e referenced to ground . +7.0 V dc Voltage on any digital pin. GND 0.5 V dc to VS+ 0.5 V dc Analog output short circuit duration . Indefinite Storage temperature range -65C to +150C Lead temperature (soldering, 5.0 seconds) . +260C Power dissipation (PD) . 3.025 W Thermal resistance, junction-to-cas

9、e (JC). See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA) 25C/W Junction temperature (TJ) +150C 1.4 Recommended operating conditions. Ambient operating temperature range (TA) -55C to +125C Supply voltage range (VS) 4.5 V dc to 5.5 V dc Reference voltage range (VREF). 1.20 V dc to 1.26 V

10、dc CLOCK and CLOCK only: Input high voltage range (VIH). VS 1.0 V dc to VS+ 0.5 V dc Input low voltage range (VIL) GND 0.5 V dc to VS 1.6 V dc Differential voltage (VDIFF) 600 mV minimum Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROC

11、IRCUIT DRAWING SIZE A 5962-89928 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing t

12、o the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - T

13、est Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assi

14、st.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of

15、this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class

16、level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with

17、 the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. Th

18、ese modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be a

19、s specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 2. 3.2.3

20、Truth tables. The truth tables shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical te

21、st requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962

22、-89928 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxOutput resolution RES 1,

23、 2, 3 01 8.0 Bits Integral linearity error ILE 1, 2, 3 01 1.0 LSB Differential linearity error DLE Guaranteed monotonic to 8.0 bits 1, 2, 3 01 1.0 LSB Gray scale error GSE 1, 2, 3 01 5.0 % gray scale Digital input high voltage VIHExcept CLOCK and CLOCK 1, 2, 3 01 2.0 V Digital input low voltage VILE

24、xcept CLOCK and CLOCK 1, 2, 3 01 0.8 V Input high current (All digital inputs) IIHVIN= 2.4 V 1, 2, 3 01 10 A Input high current (D0 D7) VIN= 5.5 V, VS= 5.5 V 10 Input high current (CLOCK and CLOCK ) VIN= 4.5 V and 5.5 V 10 Input low current (All digital inputs) IILVIN= 0.8 V 1, 2, 3 01 -10 A Input l

25、ow current (D0 D7) VIN= 0.0 V, VS= 5.5 V -10 Input low current (CLOCK and CLOCK ) VIN= 0.0 V -10 Digital output high voltage VOHIOH= -800 A 1, 2, 3 01 2.4 V Digital output low voltage VOLIOL= 6.4 mA 1, 2, 3 01 0.4 V Output high impedance current IOZ1, 2, 3 01 10 A Analog output current IAOWhite leve

26、l relative to blank 1, 2, 3 01 17.69 20.40 mA White level relative to black 16.74 18.50 Black level relative to blank 0.95 1.90 Blank level on IOR, IOB -10 50 A Blank level IOG 6.29 8.96 mA Sync level on IOG -10 50 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or netw

27、orking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89928 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherw

28、ise specified Group A subgroups Device type Limits Unit Min MaxDAC to DAC matching 2/ DDM 1, 2 01 5.0 % 3 7. Output compliance voltage VOC1, 2, 3 01 -1.0 +1.2 V Supply current ISVS= 5.5 V, f = 110 MHz, TA= -55C 3 01 550 mA Input capacitance CINSee 4.3.1c 4 01 20 pF Output capacitance COUTSee 4.3.1c

29、4 01 20 pF Clock and data feedthrough 3/ CDF See 4.3.1c 4 01 -23 dB Maximum clock rate 4/ fMAX10 01 110 MHz Maximum LD rate 4/ LDMAX10 01 27.5 MHz WR/ , C0, and C1 setup time t1See figures 4 and 5 9, 10, 11 01 0 ns WR/ , C0, and C1 hold time t29, 10, 11 01 15 ns CE low time t39, 10, 11 01 50 ns CE h

30、igh time t49, 10, 11 01 25 ns CE asserted to data bus driven t59, 10, 11 01 8.0 ns CE asserted to data valid t69, 10, 11 01 75 ns CE negated to high impedance data bus t79, 10, 11 01 15 ns Write data setup time t89, 10, 11 01 35 ns Write data hold time t99, 10, 11 01 3.0 ns Pixel and control setup t

31、ime t109, 10, 11 01 3.0 ns Pixel and control hold time t119, 10, 11 01 2.0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89928 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO

32、 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxClock cycle time t12See figures 4 and 5 9, 10, 11 01 9.09 ns Clock pulse wid

33、th high time t139, 10, 11 01 4.0 ns Clock pulse width low time t149, 10, 11 01 4.0 ns LD cycle time 4/ t1510 01 36.36 ns LD pulse width high time t16 9, 10, 11 01 15 ns LD pulse width low time t179, 10, 11 01 15 ns Analog output rise and fall times 4/ t1810 01 4.0 ns 1/ Unless otherwise specified, a

34、ll measurements are made at VS= 4.5 V and 5.5 V, RSET= 523 0.1%, and VREF= 1.235 V. TTL input values are 0 V to 3.0 V, with input rise and fall times 3.0 ns, measured between the 10 percent and 90 percent points. ECL input levels are VS 0.8 V to VS+ 1.8 V, with input rise and fall times 2.0 ns, meas

35、ured between the 20 percent and 80 percent points. Analog output is loaded with a doubly terminated line. D0 D7 output load is approximately 75 pF. 2/ DAC to DAC matching is computed by: (max reference white min reference white) X 100 max reference white 3/ Derived from characterization (TA= +25C, V

36、S= 5.0 V 10%), not tested. These parameters are controlled via design or process parameters and are not directly tested. They are characterized upon initial design release and upon design changes which could affect them. 4 Tested at TA= +125C and VS= 4.5 V. Provided by IHSNot for ResaleNo reproducti

37、on or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89928 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol Terminal numb

38、er Terminal symbol A1 OL0A C11 VSK3 P2A A2 D3 C12 VSK10 P4D A3 D4 D1 OL1A K11 P5A A4 D6 D2 OL0E K12 P5C A5 CE D11 P7E L1 P1C A6 GND D12 P7D L2 P1E A7 VSE1 OL1C L3 P2C A8 C1 E2 OL1B L4 P3A A9 VSE11 P7C L5 P3C A10 IOG E12 P7B L6 P3E A11 IOB F1 OL1D L7 VSA12 COMP F2 OL1E L8 CLK B1 OL0C F11 P7A L9 BLK B

39、2 D1 F12 P6E L10 P4B B3 D2 G1 P0A L11 P4C B4 D5 G2 P0B L12 P5B B5 D7 G11 P6D M1 P2B B6 GND G12 P6C M2 P2D B7 CO H1 P0C M3 P2E B8 WR/ H2 P0D M4 P3B B9 IOR H11 P6A M5 P3D B10 FS ADJ H12 P6B M6 GND B11 GND J1 P0E M7 VSB12 GND J2 P1A M8 CLK C1 OL0D J11 P5D M9 LD C2 OL0B J12 P5E M10 SYNC C3 D0 K1 P1B M11

40、 P4A C10 VREFK2 P1D M12 P4E FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89928 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 22

41、34 APR 97 FIGURE 2. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89928 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 Description IOG

42、 (mA) IOR, IOB (mA) SYNC BLK DAC Input data WHITE 26.67 19.05 1 1 *FF DATA data + 9.05 data + 1.44 1 1 data DATA-SYNC data + 1.44 data + 1.44 0 1 data BLACK 9.05 1.44 1 1 *00 BLACK-SYNC 1.44 1.44 0 1 *00 BLANK 7.62 0 1 0 *XX SYNC 0 0 0 0 *XX Video output NOTES: 1. Typical with full scale IOG = 26.67

43、 mA. RSET = 523, VREF= 1.235 V. 2. * denotes hex symbol. CR6 OL1 OL0 P7 P0 Addressed by frame buffer 1 0 0 $00 color palette entry $00 1 0 0 $01 color palette entry $01 : : : : : 1 0 0 $FF color palette entry $FF 0 0 0 $XX overlay color 0 X 0 1 $XX overlay color 1 X 1 0 $XX overlay color 2 X 1 1 $XX

44、 overlay color 3 Palette and overlay select FIGURE 3. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89928 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 10 DSC

45、C FORM 2234 APR 97 Value C1 C0 Addressed by MPU ADDRa, b (counts modulo 3) 00 X 1 red value 01 green value 10 X 1 blue value ADDR0 7 (counts binary) $00 - $FF 0 1 color palette RAM $00 1 1 overlay color 0 $01 1 1 overlay color 1 $02 1 1 overlay color 2 $03 1 1 overlay color 3 $04 1 0 read mask regis

46、ter $05 1 0 blink mask register $06 command register $07 1 0 test register Address register (ADDR) operation WR/ C1 C0 ADDRb ADDRa 0 0 0 X X write address register; D0-D7 - ADDR0-7, 0 - ADDRa, ADDRb 0 0 1 0 0 write red color; D0-D7 - RREG, increment ADDRa-b 0 0 1 0 1 write green color; D0-D7 - GREG,

47、 increment ADDRa-b 0 0 1 1 0 write blue color; D0-D7 - BREG, write color palette RAM, increment ADDR0-7, increment ADDRa-b 0 1 0 X X write to control register; D0-D7 - reg(ADDR), 0 - ADDRa, ADDRb 0 1 1 0 0 write red color; D0-D7 - RREG, increment ADDRa-b 0 1 1 0 1 write green color; D0-D7 - GREG, in

48、crement ADDRa-b 0 1 1 1 0 write blue color; D0-D7 - BREG, write overlay register, increment ADDR0-7, increment ADDRa-b 1 0 0 X X read address register; ADDR0-7 - D0-D7, 0 - ADDRa, ADDRb 1 0 1 0 0 read color palette red; R0-R7 - D0-D7, increment ADDRa-b 1 0 1 0 1 read color palette green; G0-G7 - D0-D7, increment ADDRa-b 1 0 1 1 0 read color palette blue; B0-B7 - D0-D7, increment ADDR0-7, Increment ADDRa-b 1 1 0 X X read control register; reg(ADDR)