1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Updated boilerplate. Added provisions for the supply of QD certified parts to the drawing. Added CAGE 0EU86 to drawing. - glg 00-08-30 Raymond Monnin B Boilerplate update and part of five year review. tcr 07-07-06 Robert M. Heber THE ORIGINAL FIRST PAGE OF
2、THIS DRAWING HAS BEEN REPLACED. REV SHEET B B REV 15 16 SHEET REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Jeffery D. Bowling DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-39
3、90 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Michael. A. Frye MICROCIRCUITS, MEMORY, DIGITAL, CMOS, 64K x 4 SRAM WITH SEPARATE I/O, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-10-30 AMSC N/A REVISION LEVEL B SIZE
4、 A CAGE CODE 67268 5962-89935 SHEET 1 OF 16 DSCC FORM 2233 APR 97 5962-E400-07 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89935 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B S
5、HEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN shall be as shown in the following example:
6、5962-89935 01 X A | | | | | | | | | | | | Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit Access time 01 7C192 64K X 4 SRAM Separate I/O
7、 45 ns 02 7C192 64K X 4 SRAM Separate I/O 35 ns 03 7C192 64K X 4 SRAM Separate I/O 25 ns 1.2.2 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835, and as follows: Outline letter Descriptive designator Terminals Package style X CDIP3-T28 or GDIP4-T28 28 dual in-line Y GDFP2-F
8、28 28 flat pack Z CQCC4-N28 28 rectangular leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage to ground potential . -0.5 V dc to +7.0 V dc DC voltage applied to outputs in High-Z state -0.5 V dc to +7.0
9、V dc DC input voltage. -3.0 V dc to +7.0 V dc DC output current 20 mA Maximum power dissipation (PD): 2/ 1.0 W Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Storage temperature range -65C to +150 Junction temperature (TJ) 1/ +150C 1.4 Rec
10、ommended operating conditions. Case operating temperature range (TC). -55C to +125C Input low voltage (VIL) 0.8 V dc maximum Input high voltage (VIH) 2.2 V dc minimum Supply voltage range (VCC) +4.5 V dc to +5.5 V dc GND voltage (GND) . 0 V dc _ 1/ Maximum junction temperature may be increased to +1
11、75 C during burn-in and steady-state life. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89935 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 2. APPL
12、ICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPART
13、MENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDB
14、K-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Phil
15、adelphia, PA 19111-5094.) 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIAL
16、S (ASTM) ASTM Standard F1192-00 - Standard Guide for the Measurement of Single Event Phenomena (SEP) induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohoc
17、ken, PA 19428-2959; http:/www.astm.org.) ELECTRONICS INDUSTRIES ALLIANCE (EIA) JEDEC Standard EIA/JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standar
18、ds and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and t
19、he references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDA
20、RD MICROCIRCUIT DRAWING SIZE A 5962-89935 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B dev
21、ices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufa
22、cturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modific
23、ations shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. This drawing has been modified to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.
24、3.2.2 of MIL-PRF-38535 or other alternative approved by the qualifying activity. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections sh
25、all be as specified on figure 1. 3.2.2 Truth table. The truth table shall be as specified on figure 2. 3.2.3 Case outlines. The case outlines shall be in accordance with figure 1 and 1.2.2 herein. 3.2.4 Functional tests. Various functional tests used to test this device are contained in the appendix
26、. If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing or acquiring activity upon request. 3.2.5
27、Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only. Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the internal moisture content test at 5000 ppm (see method
28、 1018 of MIL-STD-883). The frequency of the internal water vapor testing shall not be decreased unless approved by the preparing activity. Samples may be pulled anytime after seal. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristi
29、cs are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall
30、be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking th
31、e “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to
32、identify when the QML flow option is used. For product built in accordance with A.3.2.2 of MIL-PRF-38535, or as modified in the manufacturers QM plan, the “QD” certification mark shall be used in place of the “Q” or “QML” certification mark. 3.6 Certificate of compliance. A certificate of compliance
33、 shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL
34、-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be
35、 required for any change that affects this drawing 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the revi
36、ewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89935 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characterist
37、ics. Test Symbol Conditions 1/ -55C TC+125C 4.5 V VCC 5.5 V Group A subgroups Device types Limits Unit unless otherwise specified Min Max Output high voltage VOHVCC= 4.5 V, IOH= -4.0 mA VIN= VIH, VIL1, 2, 3 All 2.4 V Output low voltage VOLVCC= 4.5 V, IOL= 8.0 mA VIN= VIH, VIL1, 2, 3 All 0.4 V Input
38、high voltage 2/ VIH1, 2, 3 All 2.2 V Input low voltage 2/ VIL1, 2, 3 All 0.8 V Input leakage current IIXVIN= 5.5 V to GND 1, 2, 3 All -10 10 A Output leakage current IOZVCC= 5.5 V, VOUT= 5.5 V and GND 1, 2, 3 All -10 10 A Operating supply current 3/ ICC1VCC= 5.5 V, IOUT= 0 mA CE = VIL, f = fMAX1, 2,
39、 3 All 130 mA Standby power supply current TTL 3/ ICC2VCC= 5.5 V, CE VIH, all other inputs VIH, IOUT= 0 mA, f = fMAX1, 2, 3 All 40 mA Standby power supply current CMOS ICC3CE (VCC-0.3 V), all other inputs (VCC-0.3 V), VCC= 5.5 V, f = 0 1, 2, 3 All 20 mA Input capacitance 4/ CINVCC= 5.0 V TA= +25C, f
40、 = 1 MHz (see 4.3.1c) 4 All 10 pF Output capacitance 4/ COUTVCC= 5.0 V TA= +25C, f = 1 MHz (see 4.3.1c) 4 All 10 pF Functional tests see 4.3.1d 7,8 All 01 45 02 35 Read cycle time tAVAV9, 10, 11 03 25 ns 01 45 02 35 Address access time tAVQV9, 10, 11 03 25 ns Output hold from address change tAVQX9,
41、10, 11 All 3 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89935 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TAB
42、LE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TC+125C 4.5 V VCC 5.5 V Group A subgroups Device types Limits Unit unless otherwise specified Min Max 01 45 02 35 Chip enable access time tELQV9, 10, 11 03 25 ns Chip enable to output active 4/ 5/ tELQX9, 10, 11
43、 All 3 ns 01 20 02 15 Chip select to output inactive 4/ 5/ tEHQZ9, 10, 11 03 13 ns Chip enable to power up 4/ tELPU9, 10, 11 All 0 ns 01 45 02 35 Chip enable to power down 4/ tEHPD9, 10, 11 03 25 ns 01 45 02 35 Write cycle time tAVAV9, 10, 11 03 25 ns 01 40 02 30 Chip enable to write end 4/ tELWH tE
44、LEH9, 10, 11 03 20 ns 01 35 02 25 Address setup to end of write tAVWH tAVEH9, 10, 11 03 20 ns Address hold from write end tWHAX tEHAX9, 10, 11 All 0 ns Address setup to write start tAVWL tAVEL9, 10, 11 All 0 ns 01 30 02 25 Write enable pulse width tWLWH tWLEH9, 10, 11 03 20 ns See footnotes at end o
45、f table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89935 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance character
46、istics - continued. Test Symbol Conditions 1/ -55C TC+125C 4.5 V VCC 5.5 V Group A subgroups Device types Limits Unit unless otherwise specified Min Max 01 20 02 17 Data setup to write end tDVWH tDVEH 9, 10, 11 03 15 ns Data hold from write end tWHDX tEHDX 9, 10, 11 All 0 ns Write enable high to out
47、put active 4/ 5/ tWHQX9, 10, 11 All 0 ns 01 20 02 15 Write enable low to output inactive 4/ 5/ tWLQZ9, 10, 11 03 13 ns 1/ AC measurements assume signal transition times of 5 ns, input levels of 0 V to 3.0 V, and output loading of 30 pF. Output timing reference level is 1.5 V. See figure 3 (circuit A). 2/ These are absolute values with respect to device ground and all overshoots and undershoots due to system or tester n
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