DLA SMD-5962-89948 REV G-2008 MICROCIRCUIT MEMORY DIGITAL CMOS 2000 GATE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Redraw with changes. Converted drawing to one part-one number SMD format. Added package, outline letters Z and U. Added devices 03 and 04. 93-09-14 Michael A. Frye B Added case outline T. Made format changes, editorial changes throughout 93-11-19

2、 Michael A. Frye C Added case outlines M, N, and 9. Editorial changes throughout. 94-06-06 Michael A. Frye D Changes in accordance with NOR 5962-R008-96. 95-11-03 Michael A. Frye E Changes in accordance with NOR 5962-R004-97. 96-10-04 Ray Monnin F Update drawing to current requirements. Editorial ch

3、anges throughout. - gap 02-02-01 Ray Monnin G Boilerplate update, part of 5 year review. ksr 08-05-16 Robert M. Heber REV SHET REV G G G G G G G G G G G G G G G G G G G G SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV G G G G G G G G G G G G G G OF SHEETS SHEET 1 2

4、3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Rajesh Pithadia COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye AND AGENCIES OF THE

5、 DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-07-29 MICROCIRCUIT, MEMORY, DIGITAL, CMOS 2000 GATE, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON AMSC N/A REVISION LEVEL G SIZE A CAGE CODE 67268 5962-89948 SHEET 1 OF 34 DSCC FORM 2233 APR 97 5962-E356-08 Provided by IHSNot for ResaleNo reproduction

6、or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89948 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of hig

7、h reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN.

8、 The PIN is as shown in the following example: 5962 - 89948 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RH

9、A marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2

10、Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Toggle Speed 01 3020-50 8 x 8 2000 gate programmable array 50 MHz 02 3020-70 8 x 8 2000 gate programmable array 70 MHz 03 3020-100 8 x 8 2000 gate programmable array 100 MHz 04 30

11、20-125 8 x 8 2000 gate programmable array 125 MHz 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant

12、, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA

13、15-PN 84 1/ Pin grid array package Y See figure 1 100 Quad flat package Z CMGA3-PN 84 1/ Pin grid array package U CQCC1-F100 100 Unformed-lead chip carrier 2/ T See figure 1 100 Quad flat package M See figure 1 100 Quad flat package N See figure 1 100 Quad flat package 9 See figure 1 100 Quad flat p

14、ackage 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1/ 84 = actual number of pins used, not maximum listed in MIL-STD-1835. 2/ Pin 1 is the middle pin on the side with center justified identifier mark.

15、 Mark may be a notch, dot, or triangle. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89948 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolu

16、te maximum ratings. 3/ Supply voltage range to ground potential (VCC) -0.5 V dc to +7.0 V dc DC input voltage range . -0.5 V dc to VCC+0.5 V dc Voltage applied to three-state output (VTS) . -0.5 V dc to VCC+0.5 V dc Lead temperature (soldering, 10 seconds) . +260C Thermal resistance, junction-to-cas

17、e (JC): Case outline X, Z, and U See MIL-STD-1835 Case outlines Y, T, M, N, and 9 . 10C/W 4/ Junction temperature (TJ) . +150C 5/ Storage temperature range . -65C to +150C 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests in accordance with

18、 MIL-PRF-38535. 95 percent 1.4 Recommended operating conditions. 6/ Case operating temperature range (TC) -55C to +125C Supply voltage relative to ground (VCC) +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) or (VSS) . 0 V dc 2. APPLICABLE DOCUMENTS 2.1 Government specification, standard

19、s, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrate

20、d Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDB

21、K-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publicatio

22、ns. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation. ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 - IC Latch-Up Test. (Applications for copies sh

23、ould be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be availabl

24、e in or through libraries or other informational services.) _ 3/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 4/ When a thermal resistance for this case is specified in MI

25、L-STD-1835 that value shall supersede the value indicated herein. 5/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 6/ All voltage values in this drawing are with respect to VSS. Provi

26、ded by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89948 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 4 DSCC FORM 2234 APR 97 2.3 Order of precedence. In the event of a conflict bet

27、ween the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requiremen

28、ts for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements f

29、or device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes

30、 Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Logic block diagram. The logic block diagra

31、m shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case oper

32、ating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufact

33、urers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device cl

34、asses Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark

35、for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.7.1 herein). For dev

36、ice class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.7.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm t

37、hat the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PR

38、F-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this d

39、rawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be

40、 made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). 3.11 Operational notes. Additional information shall be provided by t

41、he device manufacturer (see 6.6 herein). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89948 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 5 DSCC FORM 2234 APR 97 4. VERIFI

42、CATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as describ

43、ed herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conform

44、ance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Delete the sequence specified as initial (pre-burn-in) electrical par

45、ameters through interim (post-burn-in) electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein. b. Burn-in test, method 1015 of MIL-STD-883. (1) The test circuit shall be maintained by the manufacturer under document revision level control and shall be made availabl

46、e to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015. (2) TA= +125C, minimum. c. Interim and final electrical test parameters shall be as specifi

47、ed in table IIA herein. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturers QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be main

48、tained under document revision level control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation,

49、as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device c