DLA SMD-5962-89956 REV C-2009 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED LOW POWER SCHOTTKY TTL OCTAL BUS TRANSCEIVERS AND REGISTERS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes IAW NOR 5962-R206-92. Editorial changes. -tvn 92-05-11 Tim H. Noh B Update to reflect latest changes in format and requirements. Editorial changes throughout. -les 02-06-10 Raymond Monnin C Update drawing to current requirements. Editoria

2、l changes throughout. - gap 09-08-05 Charles F. Saffle The original first sheet of this drawing has been replaced. REV SHET REV SHET REV STATUS REV C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Larry T. Gauder DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43

3、218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Tim H. Noh APPROVED BY William K. Heckman MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED LOW POWER SCHOTTKY TTL, OCTAL BUS TRANSCEIVERS AN

4、D REGISTERS, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-10-26 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-89956 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E177-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING

5、SIZE A 5962-89956 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Pa

6、rt or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89956 01 L X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number

7、Circuit function 01 54ALS646 Octal bus transceivers and registers with non-inverting 3-state outputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 Dual-in-line pac

8、kage K GDFP2-F24 or CDFP3-F24 24 Flat package 3 CQCC1-N28 28 Square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage . -0.5 V dc to +7.0 V dc Input voltage -1.5 V dc at -18 mA to +7.0 V dc Off-state output volt

9、age . +5.5 V dc Lead temperature (soldering, 10 seconds) +300C Junction temperature (TJ) +175C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Storage temperature range -65C to +150C Maximum power dissipation (PD) 1/ 358 mW 1/ Supply voltage range (VCC) 4.5 V dc to 5.5 V dc Minimum high

10、 level input voltage (VIH) 2.0 V dc Maximum low level input voltage (VIL) . 0.7 V dc Maximum high level output current (IOH) -1.0 mA Maximum low level output current (IOL): QHoutput . 8 mA Q output . 12 mA _ 1/ Must withstand the added PDdue to short circuit test (e.g. IOS). Provided by IHSNot for R

11、esaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89956 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Case operating temperature range (TC

12、) -55C to +125C Pulse duration, clocks high or low (tW) 14.5 ns minimum Setup time, A before CAB or B before CBA (tS) . 15.0 ns minimum Hold time, A after CAB or B after CBA (tH) 01.0 ns minimum 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specificati

13、on, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specific

14、ation for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Co

15、pies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the referenc

16、es cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535,

17、appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as Q

18、ML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit,

19、or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without licen

20、se from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89956 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PR

21、F-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Test circuit and switch

22、ing waveforms. The test circuit and switching waveforms shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full (case or ambient) operating t

23、emperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked wit

24、h the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A co

25、mpliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of comp

26、liance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers pr

27、oduct meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notific

28、ation of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made availab

29、le onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89956 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I.

30、 Electrical performance characteristics. Test Symbol Conditions -55C TC+125C Group A subgroups Limits Unit unless otherwise specified 1/ Min Max High level output voltage VOH VCC= 4.5 V VIL= 0.8 V IOH= -0.4 mA, 1, 3 2.5 V VIH= 2.0 V VIL= 0.7 V 2 2.5 V 2/ VIL= 0.8 V IOH= -3.0 mA, 1, 3 2.4 V VIL= 0.7

31、V 2 2.4 V VIL= 0.8 V IOH= -12 mA, 1, 3 2.0 V VIL= 0.7 V 2 2.0 V Low level output voltage VOL VCC= 4.5 V VIH= 2.0 V VIL= 0.8 V 1, 3 0.4 V IOL= 12 mA 2/ VIL= 0.7 V 3 0.4 V Input clamp voltage VI CVCC= 4.5 V, IIN= -18 mA 1, 2, 3 -1.2 V High level input current II H1 VCC= 5.5 V VIN= 7.0 V Control inputs

32、 1, 2, 3 0.1 mA 3/ VIN= 5.5 V A or B ports 0.1 mA II H2 VIN= 2.7 V Control inputs 20 A A or B ports 20 A Low level input current IILVCC= 5.5 V Control inputs 1, 2, 3 -0.2 mA VIN= 0.4 V A or B ports 1, 2, 3 -0.2 mA Output current IO VCC= 5.5 V, VOUT= 2.25 V 4/ 1, 2, 3 -20 -112 mA Supply current ICCHV

33、CC= 5.5 V Outputs high 1, 2, 3 76 mA ICCLOutputs low 1, 2, 3 88 mA CCZOutputs disabled 1, 2, 3 88 mA Functional tests See 4.3.1c 5/ 7, 8 Maximum frequency fMAX VCC= 4.5 V to 5.5 V CL= 50 pF R1= 500 R2= 500 See figure 3 6/ 9, 10, 11 35 MHz Propagation delay time, CBA, CAB to An, Bn tPLH1 9, 10, 11 10

34、 35 ns tPHL1 5 20 ns Propagation delay time, An, Bn to Bn, An tPLH2 9, 10, 11 5 22 ns tPHL2 3 15 ns Propagation delay time, SBA, SAB to An, Bn (with An,Bn low) 7/ tPLH3 9, 10, 11 10 40 ns tPHL3 5 23 ns See footnotes at end of table.Provided by IHSNot for ResaleNo reproduction or networking permitted

35、 without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89956 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC+125C Group A subgroups Lim

36、its Unit unless otherwise specified 1/ Min Max Propagation delay time, SBA, SAB to An, Bn (with An,Bn high) 7/ tPLH4 VCC= 4.5 V to 5.5 V CL= 50 pF R1= 500 R2= 500 See figure 3 6/ 9, 10, 11 8 30 ns tPHL4 5 24 ns Enable time, G to An, Bn tPZH1 9, 10, 11 3 20 ns tPZL1 5 22 ns Disable time, G to An, Bn

37、tPHZ1 9, 10, 11 1 12 ns tPLZ1 1 20 ns Enable time, DIR to An, Bn tPZH2 9, 10, 11 5 38 ns tPZL2 5 30 ns Disable time, DIR to An, Bn tPHZ2 9, 10, 11 1 12 ns tPLZ2 2 21 ns 1/ Unused inputs that do not directly control the pin under test must be put at 2.5 V or 0.4 V. No unused inputs shall be floated.

38、2/ All outputs must be tested. In the case where only one input at VILmaximum or VIHminimum produces the proper state, the test must be performed with each input being selected as the VILmaximum or VIHminimum input. 3/ For I/O ports, the parameters IIH2and IILinclude the off-state output current. 4/

39、 The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit output current, IOS. Not more than one output will be tested at one time and duration of the test condition shall not exceed one second. 5/ Functional tests shall be conducted at

40、 input test conditions of GND VIL VOLand VOH VIH VCC. 6/ Propagation delay limits are based on single output switching. Unused inputs = 3.5 V or 0.3 V. 7/ These parameters are measured with the internal output state of the storage register opposite to that of the bus input. Provided by IHSNot for Re

41、saleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89956 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines K and L 3 Terminal number Terminal symbols 1 C

42、AB NC 2 SAB CAB 3 DIR SAB 4 A1 DIR 5 A2 A1 6 A3 A2 7 A4 A3 8 A5 NC 9 A6 A4 10 A7 A5 11 A8 A6 12 GND A7 13 B8 A8 14 B7 GND 15 B6 NC 16 B5 B8 17 B4 B7 18 B3 B6 19 B2 B5 20 B1 B4 21 G B3 22 SBA NC 23 CBA B2 24 VCCB1 25 G 26 SBA 27 CBA 28 VCCNC = No connection FIGURE 1. Terminal connections. Provided by

43、 IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89956 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 Inputs Data I/O Operation mode G DIR CAB CBA SAB SBA A1 THRU

44、A8 B1 THRU B8 X X X X X Input Unspecified 1/ Store A, B unspecified 1/ X X X X X Unspecified 1/ Input Store B, A unspecified 1/ H X X X Input Input Store A and B data H X H/LX H/L X X Input Input Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H/L X H Output Input St

45、ored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H/L X H X Input Output Stored A data to B bus H = High logic level L = Low logic level = Transition from a low to a high logic level X = Irrelevant H/L = High or low logic level 1/ The data output functions may be enabled or

46、 disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every low to high transition on the clock inputs. FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr

47、om IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89956 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 FIGURE 3. Test circuit and switching waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

48、 IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89956 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 10 DSCC FORM 2234 APR 97 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by output control. 3. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by o