DLA SMD-5962-90510 REV A-2006 MICROCIRCUIT DIGITAL HCMOS 8-BIT MICROCONTROLLER WITH 256 BYTES RAM AND 512 BYTES EEPROM MONOLITHIC SILICON《硅单片 装有256字节随机存取存储器 512字节电可擦除只读存储器的8位微处理器 H.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to current MIL-PRF-38535 requirements. - CFS 06-11-01 Thomas M. Hess REV A SHET 35 REV A A A A A A A A A A A A A A A A A A A A SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV A A A A A A A A A A

2、 A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Chris A. Rauch DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Thomas M. Hess COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Monic

3、a L. Poelking MICROCIRCUIT, DIGITAL, HCMOS, 8-BIT MICROCONTROLLER WITH 256 BYTES RAM AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-03-30 AND 512 BYTES EEPROM, MONOLITHIC SILICON AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268 5962-90510 A SHEET 1 OF 35 DSCC FORM 2233 APR 97 5962-

4、E033-07 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90510 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes

5、 device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-90510 01 X X Drawing number Device type (see 1.2.1) Case outline(see 1.2

6、.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 68HC11A0 HCMOS, 8-bit microcontroller, ROM and EEPROM disabled, 256 bytes RAM 02 68HC11A1 HCMOS, 8-bit microcontroller, ROM disabled, 256 bytes

7、RAM, 512 bytes EEPROM 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T48 or CDIP2-T48 48 Dual-in-line Y See figure 1 52 Gullwing lead chip carrier 1.2.3 Lead finish. The lead finish is

8、 as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range (VDD). -0.3 V dc to +7.0 V dc Storage temperature range (Tstg) -65C to +150C Maximum power dissipation (PD) 210 mW 1/ Lead temperature (soldering, 5 seconds) . 270C Maximum junction temperature (TJ) 150C T

9、hermal resistance, junction-to-case (JC): Case X. See MIL-STD-1835 Case Y. 10C/W 1.4 Recommended operating conditions. Supply voltage range (VDD). 4.5 V dc minimum to 5.5 V dc maximum High level input voltage (VIH). 0.8 x VDDLow level input voltage (VIL) VSSto 0.2 x VDDMaximum high level output volt

10、age (VOH) . VDD 0.1 V Maximum low level output voltage (VOL) . 0.4 V Case operating temperature range (TC) -55C to +125c Frequency of operation. 1.0 MHz to 2.1 MHz _ 1/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitt

11、ed without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90510 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standar

12、ds, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

13、DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of the

14、se documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawin

15、g and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance wi

16、th MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may

17、 be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not

18、affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, c

19、onstruction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Function

20、al block diagram. The functional block diagram shall be as specified on figure 3. 3.2.4 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical perf

21、ormance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provid

22、ed by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90510 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF

23、-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the d

24、evice. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the

25、QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source

26、of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to t

27、his drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentati

28、on. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Processing EEPROMS. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.10.1 Erasure of EEPROM. When specified, devices shall be era

29、sed in accordance with the procedures and characteristics prior to delivery. 3.10.2 Programmability of EEPROM. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.4. 3.10.3 Verification of erasure or programmability of EEPROM.

30、When specified, devices shall be verified as either programmed to the specified pattern, or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall cons

31、titute a device failure, and shall be removed from the lot. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90510 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 22

32、34 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Group A subgroups Device type Limits Unit Conditions -55C TC +125C 4.5 V dc VDD 5.5 V dc VSS= 0.0 V dc unless otherwise specified Min Max Output high voltage, all outputs except RESET, XTAL, and MODA VOHIOH= -0.8 mA VDD= 4.5 V dc

33、 1/ VDD 0.8 V Output low voltage, all outputs except XTAL VOLIOL= 1.6 mA 0.4 V All inputs except RESET 0.7 x VDDVDDInput high voltage RESET VIH0.8 x VDDVDDV Input low voltage, all inputs VILVSS0.2 x VDDV I/O ports, three-state leakage PA7, PC0-PC7, PD0-PD5, AS/STRA, MODA/LIR, RESET IOZVIN= VIHor VIL

34、10 A VIN= VDD0.0 +1.0 PA0-PA2, PA3, IRQ, XIRQ VIN= VSS-1.0 VIN= VDD0.0 +10 Input current 2/ MODB/VSTBY IINVIN= VSSVDD= 5.5 V 0.0 -10 A RAM standby voltage powerdown VSB4.0 VDDV RAM standby current powerdown ISB20 A Single chip mode 20 Total supply current 3/ RUN IDDExpanded multiplexed mode 30 mA Si

35、ngle chip mode 10 WAIT: All peripheral functions shut down. WIDDExpanded multiplexed mode 15 mA Total supply current STOP: No clocks. SIDDSingle chip mode 1, 2, 3 300 nA PA0-PA2, PA3, PE0-PE7, IRQ, XIRQ, EXTAL 8 Input capacitance PA7, PC0-PC7, PD0-PD5, AS/STRA, MODA/LIR, RESET CINVIN= 0.0 V, fIN= 1

36、MHz See 4.3.1b 4 All 14 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90510 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234

37、 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Group A subgroups Device type Limits Unit Conditions -55C TC +125C 4.5 V dc VDD 5.5 V dc VSS= 0.0 V dc unless otherwise specified Min Max 1.0 MHz 1.0 Frequency of operation fO2.1 MHz 2.1 MHz 1.0 MHz 1000 E clock period

38、tcyc2.1 MHz 476 ns 1.0 MHz 4.0 Crystal frequency, external oscillator (4 fO) fXTAL2.1 MHz 8.4 MHz 1.0 MHz 200 Processor control setup, tPCS= 1/4tcyc 50 ns tPCS2.1 MHz 69 ns To guarantee external reset vector. 1.0 MHz 8.0 8.0 Reset input pulse width 5/ Minimum input time, may be prompted by internal

39、reset. PWRSTLSee figure 4. Control timing 4/ 2.1 MHz 1.0 1.0 tcyc1.0 MHz 2.0 Mode programming setup time tMPS2.1 MHz 2.0 tcyc1.0 MHz 0.0 Mode programming hold time tMPH2.1 MHz 0.0 ns 1.0 MHz 2.0 Interrupt pulse width, IRQ edge sensitive mode, PWIRQ= tcyc 20 ns PWIRQ2.1 MHz 2.0 ns 1.0 MHz 4.0 Wait re

40、covery startup time tWRS2.1 MHz 4.0 tcyc1.0 MHz 1020.0 Timer pulse width, input capture, pulse accumulator input, PWTIM= tcyc+ 20 ns PWTIMSee figure 4. Control timing 2.1 MHz 496.0 ns 1.0 MHz 1.0 1.0 Frequency of operation (E clock frequency) fO2.1 MHz 2.1 2.1 MHz 1.0 MHz 1000.0 E clock period tcyc2

41、.1 MHz 476 ns 1.0 MHz 100.0 Peripheral data setup time MCU read of ports A, C, D, and E. tPDSU2.1 MHz 100.0 ns 1.0 MHz 50.0 Peripheral data hold time MCU read of ports A, C, D, and E. tPDHSee figure 4. Peripheral port timing 2.1 MHz 9, 10, 11 All 50.0 ns See footnotes at end of table. Provided by IH

42、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90510 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Tes

43、t Symbol Group A subgroups Device type Limits Unit Conditions -55C TC +125C 4.5 V dc VDD 5.5 V dc VSS= 0.0 V dc unless otherwise specified Min Max 1.0 MHz 150 MCU write to port A. 2.1 MHz 150 1.0 MHz 340 Delay time, peripheral data write tPWD= 1/2 x tCYC+ 90 ns MCU write to port B, C, and D.tPWD2.1

44、MHz 209 ns 1.0 MHz 60.0 Input data setup time (port C) tIS2.1 MHz 60.0 ns 1.0 MHz 100.0 Input data hold time (port C) tIH2.1 MHz 100.0 ns 1.0 MHz 380.0 Delay time, E fall to STRB tDEB= 1/2tCYC+ 130 ns tDEB2.1 MHz 249.0 ns 1.0 MHz 0.0 Setup time, STRA asserted to E fall 6/ tAES2.1 MHz 0.0 ns 1.0 MHz

45、100.0 Delay time, STRA asserted to port C, data output valid tPCD2.1 MHz 100.0 ns 1.0 MHz 10.0 Hold time, STRA negated to port C data tPCH2.1 MHz 10.0 ns 1.0 MHz 150.0 Three-state hold time tPCZSee figure 4. Peripheral port timing 2.1 MHz 9, 10, 11 150.0 ns Resolution RES Number of bits resolved by

46、the A/D. 8 Bits Non-linearity NLI Maximum deviation from the ideal and A/D transfer characteristics. 1/2 LSB Zero error ZER Difference between the output of an ideal and an actual A/D for zero input voltage. 1/2 LSB Full scale error FSE Difference between the output of an ideal and an actual A/D for

47、 full-scale input voltage. 1/2 LSB Total unadjusted error TUE Maximum sum of non-linearity, zero error, and full-scale error. 1/2 LSB Quantization error QTE Uncertainty due to converter resolution. 4, 5, 6 All 1/2 LSB See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or net

48、working permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90510 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Group A subgroups Device type Limits Unit Conditions -55C TC +125C 4.5 V dc VDD 5.5 V dc VSS= 0.0 V dc unless otherwise specified Min Max Absolute accuracy AAC Difference between the actual input voltage and the full-scale weighted equivalent of the binary output code, all error sources included. 1 LSB Conversion range