DLA SMD-5962-90632 REV B-2012 MICROCIRCUIT DIGITAL-LINEAR ANALOG-TODIGITAL CONVERTER 12-BIT MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. ro 01-07-10 R. Monnin B Redraw. Drawing format and paragraphs updated to meet MIL-PRF-38535 requirements. - drw 12-08-03 Charles F. Saffle REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B B

2、 B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Dan Wonnell DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKE

3、D BY Sandra Rooney APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL-LINEAR, ANALOG-TO-DIGITAL CONVERTER, 12-BIT, MONOLITHIC SILICON DRAWING APPROVAL DATE 95-05-08 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-90632 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E431-12 Provided by IHSNot for Resa

4、leNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90632 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisti

5、ng of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.

6、1.2 PIN. The PIN is as shown in the following example: 5962 - 90632 01 M L A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes

7、Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA devi

8、ce. 1.2.2 Device type. The device type identifies the circuit function as follows: Device type Generic number Circuit function 01 AD7870T 12-bit analog-to-digital converter 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follow

9、s: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outlines. The case outlines

10、 are as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 3 CQCC1-N28 28 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-

11、38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90632 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum

12、ratings. 1/ Positive supply voltage (VDD) to AGND -0.3 V dc to +7.0 V dc Negative supply voltage (VSS) to AGND . +0.3 V dc to -7.0 V dc AGND to DGND -0.3 V dc to VDD+0.3 V dc Analog input range (VIN) to AGND -15 V dc to +15 V dc Reference output voltage (REF OUT) to AGND 0 V dc to VDDDigital input v

13、oltage to DGND . -0.3 V dc to VDD+0.3 V dc Digital output voltage to DGND . -0.3 V dc to VDD+0.3 V dc Power dissipation (PD), TA= +75C . 450 mW 2/ Lead temperature (soldering, 10 seconds) +300C Storage temperature range . -65C to +150C Thermal resistance, junctionto-case (JC) See MIL-STD-1835 Therma

14、l resistance, junctionto-ambient (JA) . 120C/W 1.4 Recommended operating conditions. Positive supply voltage range (VDD) . +4.75 V dc to +5.25 V dc Negative supply voltage range (VSS) -4.75 V dc to -5.25 V dc Analog input range -3.0 V dc to +3.0 V dc Ambient operating temperature range (TA) . -55C t

15、o +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or c

16、ontract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HA

17、NDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111

18、-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ S

19、tresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Above TA= +75C, derate 10 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IH

20、S-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90632 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specifi

21、ed herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN c

22、lass level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outli

23、nes. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.3 Electrical performance characteristics and postirradiation parameter limi

24、ts. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgro

25、ups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to spa

26、ce limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with

27、MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For d

28、evice classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an appro

29、ved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38

30、535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of m

31、icrocircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime -VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification

32、 and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of th

33、e reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 81 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICRO

34、CIRCUIT DRAWING SIZE A 5962-90632 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ 2/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Re

35、solution for which no missing codes are guaranteed RES VDD= +4.75 V, VSS= -5.25 V 1, 2, 3 01 12 BITS Integral linearity error ILE VDD= +4.75 V, VSS= -5.25 V 1, 2, 3 01 1 LSB Differential linearity error DLE VDD= +4.75 V, VSS= -5.25 V 1, 2, 3 01 1 LSB Bipolar zero error BZE VDD= +4.75 V, VSS= -5.25 V

36、 1, 2, 3 01 5 LSB Positive full scale error 3/ PFSE VDD= +4.75 V, VSS= -5.25 V 1, 2, 3 01 5 LSB Negative full scale error 3/ NFSE VDD= +4.75 V, VSS= -5.25 V 1, 2, 3 01 5 LSB Signal to noise ratio 4/ SNR VDD= +4.75 V, VSS= -5.25 V, VIN= 10 kHz sine wave, fSAMPLE= 100 kHz 4, 5, 6 01 69 dB Total harmon

37、ic distortion THD VDD= +4.75 V, VSS= -5.25 V, VIN= 10 kHz sine wave, fSAMPLE= 100 kHz 4, 5, 6 01 -78 dB Peak harmonic PH VDD= +4.75 V, VSS= -5.25 V, VIN= 10 kHz sine wave, fSAMPLE= 100 kHz 4, 5, 6 01 -78 dB Intermodulation distortion 2nd and 3rd order terms IMD VDD= +4.75 V, VSS= -5.25 V, fa= 9 kHz,

38、 fb= 9.5 kHz, fSAMPLE= 50 kHz 4, 5, 6 01 -78 dB Track / hold acquisition time 5/ tACQVDD= +4.75 V, VSS= -5.25 V 4, 5, 6 01 2 s Analog input voltage VINVDD= +4.75 V, VSS= -5.25 V 1, 2, 3 01 3 V Analog input current IINVDD= +5.25 V, VSS= -5.25 V 1, 2, 3 01 500 A Voltage reference output VREFVDD= +5 V,

39、 VSS= -5 V 1 01 2.99 3.01 V Voltage reference output temperature coefficient dREF/ dT VDD= +5 V, VSS= -5 V 2, 3 01 +60 ppm/C Reference load sensitivity REF IIN= 0 to 500 A, VDD= +5 V, VSS= -5 V, reference load not changed during conversion 1, 2, 3 01 1 mV See footnotes at end of table. Provided by I

40、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90632 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol C

41、onditions 1/ 2/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Digital input capacitance 5/ CINVDD= +5 V, VSS= -5 V 4 01 10 pF Floating state output capacitance 5/ COUTVDD= +5 V, VSS= -5 V 4 01 15 pF Digital input high voltage VINHVDD= +4.75 V, VSS= -5.25

42、V 7, 8 01 2.4 V Digital input low voltage VINLVDD= +4.75 V, VSS= -5.25 V 7, 8 01 0.8 V Digital input current IINVDD= +5.25 V, VSS= -5.25 V 1, 2, 3 01 10 A Digital output high voltage VOHISOURCE= 40 A, VDD= +4.75 V, VSS= -5 V 1, 2, 3 01 4 V Digital output low voltage VOLISINK= 1.6 mA, VDD= +4.75 V, V

43、SS= -5 V 1, 2, 3 01 0.4 V Floating state leakage current ILKGVDD= +5.25 V, VSS= -5.25 V, DB11- DB0 1, 2, 3 01 10 A Positive supply current IDDVDD= +5.25 V, VSS= -5.25 V 1, 2, 3 01 13 mA Negative supply current ISSVDD= +5.25 V, VSS= -5.25 V 1, 2, 3 01 6 mA Conversion time tCONVVDD= +5 V, VSS= -5 V, e

44、xternal clock = 2.5 MHz 9, 10, 11 01 8 s VDD= +5 V, VSS= -5 V, internal clock 6.5 9 CONVST pulse width t15/, 6/, 7/, 8/ 9, 10, 11 01 50 ns CS to RD setup t2Mode 1, 5/, 6/, 7/, 8/ 9, 10, 11 01 0 ns RD pulse width t3 6/, 7/, 8/ 9,10,11 01 75 ns CS to RD hold t4Mode 1, 5/, 6/, 7/, 8/ 9, 10, 11 01 0 ns

45、RD to INT delay t5 5/, 6/, 7/, 8/ 9, 10, 11 01 70 ns Data access time after RD t66/, 7/, 8/, 9/ 9, 10, 11 01 70 ns Bus relinquish time after RD t76/, 7/, 8/, 10/ 9, 10, 11 01 5 50 ns HBEN to RD setup t8 5/, 6/, 7/, 8/ 9, 10, 11 01 0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo r

46、eproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90632 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions 1/ 2/ -55C

47、 TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max HBEN to RD hold t9 5/, 6/, 7/, 8/ 9,10,11 01 0 ns SSTRB to SCLK falling edge setup t105/, 6/, 7/, 8/ 9, 10, 11 01 100 ns SCLK cycle t115/, 6/, 7/, 8/, 11/ 9, 10, 11 01 370 ns SCLK to valid data delay t12 5/, 6/, 7

48、/, 8/, 12/ 9, 10, 11 01 150 ns SCLK rising edge to SSTRB t135/, 6/, 7/, 8/ 9, 10, 11 01 20 100 ns Bus relinquish time after SCLK t145/, 6/, 7/, 8/ 9, 10, 11 01 10 100 ns CS to RD setup t15Mode 2, 5/, 6/, 7/, 8/ 9, 10, 11 01 60 ns CS to BUSY propagation delay t165/, 6/, 7/, 8/ 9, 10, 11 01 120 ns Data setup prior to BUSY t175/, 6/, 7/, 8/ 9, 10, 11 01 200 ns CS to RD hold t18Mode 2, 5/, 6/, 7/, 8/ 9, 10, 11 01 0 ns HBEN to CS setup t195/, 6/, 7/, 8/ 9, 10, 11 01 0 ns HBEN to CS hold t205/, 6/, 7/, 8/ 9, 10, 11 01 0 ns Functio