1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to MIL-PRF-38535 requirements. - CFS 05-08-03 Thomas M. Hess REV SHET REV A A A A A A A A A A A SHEET 15 16 17 18 19 20 21 22 23 24 25 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14
2、PMIC N/A PREPARED Chris Rauch DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Thomas Hess COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Monica Poelking MICROCIRCUIT, DIGITAL, CMOS, 16-BIT AND AGENCIES OF THE
3、DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-08-05 MICROPROCESSOR, MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-90678 SHEET 1 OF 25 DSCC FORM 2233 APR 97 5962-E423-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STAND
4、ARD MICROCIRCUIT DRAWING SIZE A 5962-90678 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space applicati
5、on (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 90678
6、 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA level
7、s and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit fun
8、ction as follows: Device type Generic number Circuit function fCLK 01 80C286-10 16-bit CMOS microprocessor 10 MHz 02 80C286-12 16-bit CMOS microprocessor 12.5 MHz 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device
9、class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are a
10、s designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA3-P68 68 Pin grid array Y See figure 1 68 Ceramic quad flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix
11、A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90678 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings
12、. 1/ Supply voltage (VCC) +7.0 V dc Input, output, or I/O voltage applied range . -1.0 V dc to VCC+ 1.0 V dc Junction temperature (JT). +150C Lead temperature (soldering, 10 seconds). +275C Power dissipation (PD) 1.1 W Thermal resistance, junction-to-case (JC): Case outline X See MIL-STD-1835 Case o
13、utline Y 9.5C/W 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Input rise and fall time (from 0.8 V to 2.0 V): Device type 01 . 10 ns maximum Device type 02 . 8.0 ns maximum Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Gov
14、ernment specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFIC
15、ATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard
16、 Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.
17、) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Stresse
18、s above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE
19、A 5962-90678 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in
20、the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as s
21、pecified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall
22、be in accordance with 1.2.4 herein and on figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 3. 3.2.4 Switching waveforms and test circuit. The switching wavefo
23、rms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over
24、 the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addi
25、tion, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Mar
26、king for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. Th
27、e compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.
28、1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this draw
29、ing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes
30、 Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices
31、acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore docu
32、mentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or ne
33、tworking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90678 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. See footnotes at end of table. Limits Test Symbol C
34、onditions 1/ -55C TC +125C, 4.5 V VCC 5.5 V unless otherwise specified Group A subgroupsDevice types Min Max Unit Input low voltage VILVCC= 4.5 V f = 2 MHz -0.5 0.8 V Input high voltage VIHVCC= 5.5 V f = 2 MHz 2.0 VCC+ 0.5 V CLK input low voltage VILCVCC= 4.5 V f = 2 MHz -0.5 1.0 V CLK input high vo
35、ltage VIHCVCC= 5.5 V f = 2 MHz 3.6 VCC+ 0.5 V Output low voltage VOLIOL= 2.0 mA 2/ VCC= 4.5 V 0.45 V IOH= -2.0 mA 2/ VCC= 4.5 V 3.0 V Output high voltage VOHIOH= -100 A 2/ VCC= 4.5 V VCC- 0.5 V Input leakage current IILVCC= 5.5 V 2/ Measured on pins: 29, 31, 57, 59, 61, 63, and 64 -10 +10 A Input su
36、staining current (bus hold low) IBHLVIN= 1.0 V 3/ 35 200 A Input sustaining current (bus hold high) IBHHVIN= 3.0 V 4/ -50 -400 A Input sustaining current on BUSY and ERROR pins ISLVIN= 0.0 V 5/ -30 -500 A Bus hold low overdrive IBHLO250 A Bus hold high overdrive IBHHOVCC= 5.5 V 6/ VIN= 5.5 V or 0.0
37、V -420 A Output leakage current ILOVOUT= 0.0 V or 5.5 V VCC= 5.5 V Measured on pins: 1, 7, 8, 10 through 28, 32, 33, and 34 All -10 +10 A f = 10 MHz 01 200 Active power supply current ICCVCC= 5.5 V VIN= 2.4 V or 0.40 V Outputs unloaded CL= 100 pF f = 12.5 MHz 02 220 mA Standby power supply current I
38、CCSVCC= 5.5 V, VIN= 0.0 V or 5.5 V Outputs unloaded 7/ 1, 2, 3 All 5.0 mA Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90678 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET
39、6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. See footnotes at end of table. Limits Test Symbol Conditions 1/ -55C TC +125C, 4.5 V VCC 5.5 V unless otherwise specified Group A subgroupsDevice types Min Max Unit CLK input capacitance CCLK20 pFOther input capacit
40、ance CIN10 pFInput/output capacitance CI/OfCLK= 1.0 MHz See 4.4.1c 4 20 pF Functional tests See 4.4.1d 7, 8 All 01 50 System clock period t1See figure 4. 02 40 ns 01 12 System clock low time t2Measured between the 1.0 V reference points on the clock input. See figure 4. 02 11 ns 01 16 System clock h
41、igh time t3Measured between the 3.6 V reference points on the clock input. See figure 4. 02 13 ns 01 20 Asynchronous input setup time 8/ t402 15 ns 01 20 Asynchronous input hold time 8/ t502 15 ns 01 23 RESET setup time t602 10 ns RESET hold time t7All 5 01 8 Read data setup time t802 5 ns 01 8 Read
42、 data hold time t902 4 ns 01 26 Ready setup time t1002 20 ns 01 25 Ready hold time t11See figure 4. 02 20 ns 01 5 13/ 22 Status/PEACK active delay 9/ t12a02 1 21 ns 01 3 13/ 30 Status/PEACK inactive delay 10/ t12b02 1 24 ns 01 4 13/ 35 Address valid delay 11/ t1302 1 32 ns 01 3 13/ 40 Write data val
43、id delay 11/ t14CL= 100 pF, IL= 2.0 mA See figure 4. 9, 10, 11 02 0 31 ns Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90678 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET
44、7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. 1/ The following pins are active low: BHE, BUSY, ERROR, INTA of COD/INTA, LOCK, PEACK, S0, S1, and READY. 2/ VIN= 0.8 V, 2.0 V. Relaxed input levels for VOLand VOHmay be used if separate VILand VIHtests (guaranteein
45、g threshold voltage transmission) are performed. 3/ IBHLshould be measured after lowering VINto GND and then raising to 1.0 V on the following pins: 36 through 51, 66, and 67. 4/ IBHHshould be measured after raising VINto VCCand then lowering to 3.0 V on the following pins: 4, 5, 6, 36 through 51, 6
46、6, 67, and 68. 5/ IILshould be measured after raising VINto VCCand then lowering to 0.0 V on pins 53 and 54. 6/ If not tested, then guaranteed to the limits specified in table I. 7/ ICCSshould be tested with the clock stopped in phase two of the processor clock cycle. 8/ Asynchronous inputs are INTR
47、, NMI, HOLD, PEREQ, ERROR, and BUSY. This specification is given only for testing purposes to assure recognition of a specific CLK edge. 9/ Delay from 1.0 V on the CLK to 1.5 V for minimum (HOLD time) and to 1.5 V for maximum (active delay). 10/ Delay from 1.0 V on the CLK to 1.5 V for minimum (HOLD
48、 time) and to 1.5 V for maximum (inactive delay). 11/ Delay from 1.0 V on the CLK to 1.5 V. 12/ Delay from 1.0 V on the CLK to float (no current drive) condition. 13/ Tested initially and at process and design changes. Thereafter, guaranteed, if not tested, to the limits specified in table I. 14/ De
49、lay from 1.0 V on the CLK to 1.5 V. 15/ Delay measured from address either reaching 1.5 V (valid) to status going active reaching 0.8 V or status going inactive reaching 1.5 V. Limits Test Symbol Conditions 1/ -55C TC +125C, 4.5 V VCC 5.5 V unless otherwise specified Device types Min Max Unit 01 2 13/ 47 Address/status/d
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