DLA SMD-5962-90708 REV A-1996 MICROCIRCUIT DIGITAL CMOS 8 X 8 MULTIPLIER MONOLITHIC SILICON《硅单块 8X8倍增器 互补金属氧化物半导体数字微型电路》.pdf

1、SMD-5962-9070 REV A m 9999996 0090342 179 m DEFENSE LOGISTICS AGENCY DEFENSE SUPPLY CENTER COLUMBUS 3990 EAST BROAD STREET COLUMBUS, OH 4321 6-5000 IN REPLY REFER TO: DSCC-VAC (Mr. Gauder/(DSN)850-0545/614-692-0545) OCT 2 9 5996 SUBJECT: Notice of Revision (NOR) 5962-R189-96 for Standard Microcircui

2、t Drawing (SMD) 5962-90708. Military/Industry Distribution The enclosed NOR is approved for use effective as of the date of the NOR. In accordance with MIL-STD-100 SMD holders should, as a minimum, handwrite those changes described in the NOR to sheet 1 of the subject SMD. After completion, the NOR

3、should be attached to the subject SMD for future reference. Those companies who were listed as approved sources of supply prior to this action have agreed to actions taken on devices for which they had previously provided DSCC a certificate of compliance. This is evidenced by an existing active curr

4、ent certificate of compliance on file at DSCC with a DSCC record of verbal coordination. The certificate of compliance for these devices is considered concurrence with the new revision unless DSCC is otherwise notified. DSCC has received and accepted a certificate of compliance from Logic Devices, C

5、age Code 65896 for PIN 5962-9070801XX. and vendor similar part number LMA1008DMB50. This action will be reflected in the next revision of MIL-HDBK- 103. If you have comments or questions, please contact Larry T. Gauder at (DSN)850-0545/(614)692-0545. 1 Encl 4onica L. Poeiking Chief, Custom .Microele

6、ctroncs Branch Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-NOTICE OF REVISION (NOR) MIS REVISION DESCRIBED BELOW HAS BEEN AUTHORIZED FOR THE DOCUMENT LISTED. ublicreporling,burden for,lhisclection is estimated io average 2 hours per,nsponse. indU

7、ding he time for reviewin instructions, searchin existing data ACTIVITY NO. :LEASE DO AT RETURN Y$k C8MPLETED FORM TO EIT dlslrlbulion Is unlirnlled. . - Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-i - SIZE A STANDARDIZED SMD-5462-70708 57 797979

8、6 0001279 5-m 5962-90708 1. SCOPE 1.1 Scope, This drawing describes device requirements for class B microcircuits in accordance with 1.2.1 of MIL-STD-883, “Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices“. 1.2 Part or Identifying Number (PIN), The complete PIN sha

9、ll be as shown in the following exampl e: 5962-90708 -I- I o1 I I X 7- I X 7- I I I I I I Lead tinisn per I 1 I Lase outline lievice type Drawmg numer (1.2.1) (1.2.2) MI L-M- 38510 1.2.1 Device type, The device type shall identify the circuit function as follows: Device type Generic number Circuit f

10、unction o1 TK2208J4Y 8 X 8 CMOS multiplier/accumulator 1.2.2 Case outline. The case outline shall be as designated in appendix C of MIL-K38510, and as fol 1 owc: Out1 ine letter Case outline X D-14 (48-lead, 2.435“ x .620“ x .225“), dual-in-line package 1.3 Absolute maximum ratings. Supply voltage r

11、ange (VDD) - - - - - - - - - - - - Input voltage range - - - - - - - - - - - - - - - - -0.5 V dc to +7.0 V dc -0.5 V dc to (YDD tO.5) Y dc output: Forced current Power dissipation 31 - - - - - - - - - - - - - - - Storage temperature-range - - - - - - - - - - - - - Junction temperature - - - - - - -

12、- - - - - - - - Case operating temperature range (Tc) - - - - - - - Lead temperature (soldering, 10 seconds)- - - - - - Thermal resistance, junction-to-case (el herein). 3.9 Verification and review. DESC, DESCs agent, and the acquiring activity retain the option to eview the manufacturers facllity a

13、nd applicable required documentation, hall be made available onshore at the option of the reviewer. Offshore documentation 4, QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection, Sampling and inspection procedures shall be in accordance with 4.2 Screening. Screening shall be in accordance with

14、method 5004 of MIL-STD-883, and shall be ection 4 f MIL - M 38510 to the extent specified in MIL-STD-883 (see 3.1 herein). onducte on -all- devices prior to quality conformance inspection. The following additional criteria hall apply: a. Burn-in fest, method 1015 of MIL-STO-883. (i) Test condition B

15、 or D usiny the circuit submitted with the certificate of compliance (see 3.6 herein). (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the m

16、anufacturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with ethod 5005 of MIL -STD-883 including groups A, B, C, and D inspections. riteria shall apply. The following additional DESC FORM 193A SE? 87 ii U. S. GOVERNMENT PRINTING OFFICE 19BB-549.W e Y P

17、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-I - 2/ All transitions are measured at 1.5 V level. VIH = 3 V during dynamic testing. Inputs are driven at VIL = O V and I I STANDARDIZED SIZE 1 I 1 Y DESC FORM 193A t U. S. GOVERNMENT PWNliNG OFFCk lW-S

18、9-8M SEP 87 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-70708 59 m 7799996 0003283 7 m SIZE A STANDARDIZED PREL L L L L L L L L H H 5962-90708 - TSX - L L L L H H H H L L IH IL IH IL IH IH IH IH IH IH IH IH - T SM - L L H H L L H H L L H

19、 H L L H H I I Terminal I number 12 7 13 14 15 16 17 18 19 I 10 I 11 I 12 I 13 I 14 I 15 I 16 I 17 I 18 I 19 I 20 I 21 I 22 I 23 I 24 - TSL - L H L H L H L H L H L H L H L H - Device type O1 Temi na1 syrnbol 11 ;12 ; ;: ;!a p10 TSM CLK P PREL p7 GND p4 p3 p2 P1 SUB ACC RND XO X1 x2 etminal number 25

20、 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I Terminal I symbol I I i x3 I x4 I x5 I x6 x7 I CLK X I CLK Y I I I I I I TZ I TSX I p16 I p15 I 14 I p13 i YO i6 I 17 FIGURE 1. Terminal connections. Device tvoe O1 XTP Register-Output pin Regi Ster-Output pin Regi ster-Output p

21、in Reyi Ster-Output pin Hi-Z Hi-Z Hi-Z , Hi-Z H i-Z Hi-Z Hi-Z Preload Hi-Z Preload Hi-Z Preload Hi-Z Preload H i-Z Hi-Z MSP Regi Ster-Output pin Regi Ster-Output pin Hi-Z Hi-Z Register-Output pin Regi Ster-Output pin Hi-Z Hi-Z Hi-Z Hi-Z Preload Hi-2 Preload Hi-Z Hi-Z Preload Hi-Z Preload Hi-Z Hi-Z F

22、IGURE 2. Preload truth table. L SP Regi Ster-Output pin Hi-Z Regi Ster-Output pin Hi-Z Register-Output pin Hi-Z Register-Output pin Hi-Z Hi-Z Preload Hi-Z Hi-Z Preload Hi-Z Hi-2 Preload Hi-Z Hi-Z Preload Hi-Z DESC FORM 193A SEP a7 4 U. S. GOVERNMENT PRINTING OFFICE 1W-Y-w)4 Provided by IHSNot for Re

23、saleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET 7 I DAYTON, OHIO 45444 t U. S. (MVERHMENT PRIKTINQ OFFICE: 1988-fHOg04 IESC FORM 193A SEP 87 Provided by IHSNot for ResaleNo reproduction or networking permitted without li

24、cense from IHS-,-,-SMD-5962-70708 57 9779996 0001285 O I STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON. OHIO 45444 E SIZE A 5962-90708 REVISION LEVEL SHEET 8 Device type O1 Fractional twos complement notation Binary point I O I IIIIIIII I Signal Digit value Signal Digit valu

25、e Signa Digit FIGURE 4. Input/output data formats, value I I - I U. S QOVERNMENT PRINTING OFFICE 1888-549-804 ESC FORM 193A SEP 87 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-I c STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER Dev

26、ice type O1 SIZE A 5962-90708 I REVISION LEVEL I SHEET Fractioiial unsigned magnitude notation inary point O I I Signal Digit value Signal Digit value MSP i LSP FIGURE 4. Input/output data formats - Continued. I l I 9 DAYTON, OHIO 45444 IESC FORM 193A ii U. S. GOVERNMENT PWNTING OFFICE: 1888-549-904

27、 SEP 87 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-90708 59 7979996 0003287 4 I SIZE A STAN DARDI ZED Integer twos complement notation 5962-90708 X MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 Binary point I I O

28、 REVISION LEVEL SHEET 10 FIGURE 4. Input/output data formats - Continued. value value value t U. S. QOVERNMENT PRINTINQ OFFICE 1988-549-Sil4 ESC FORM 193A SEP a7 Y Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Inteyer unsigned magni tute notati on

29、SIZE A STAN DARDI ZED Binary point I .I II I llllllll 1 IIIIIIII I O x7 1x6 1x5 1x4 1x3 1x2 1x1 1x0 I Signal Z7 (Z6 1Z5 1Z4 1Z3 122 12l 12O I Digit value I 5962-90708 P3 IP2 IP1 IPo I IlII I 23 122 121 120 I Digit value IlII Signal FIGURE 4. Input/output data formats - Continued. I DEFENSE ELECTRONI

30、CS SUPPLY CENTER DAYION. OHIO 45444 I REVISION LEVEL I SHEET 11 1 I 1 t U. S. OOVERNMEHT PAIMINO OFFICE; 1988-54PW4 DESC FORM 193A SEP a7 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5762-70708 57 m 9777776 0001287 & I J T- 7- I 4 4 A a a z a

31、c O O O -I W II: Y W STANDARDIZED MILITARY DRAWING I SIZE I I Al I 5962-90708 I SHEET DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL 12 DESC FORM 193A SEP 87 ii U. S. GOVERNMENT PWNTING OFFICE 1988-548-w)4 Provided by IHSNot for ResaleNo reproduction or networking permitted with

32、out license from IHS-,-,-4.3.1 STANDARDIZED SIZE A TABLE II. Electrical test requirements. 5962-90708 I I r i MIL-STD-883 test requirements i Subgroups i I (per-method 1 I 5005, table I) I I I I i interim electrical parameters i - i I (method 5004) I I I i Final electrical test parameters i 1*, 2, 3

33、, 7, 8,i i (method 5004) I 9, 10, 11 I I I Group A test requirements 1, 2, 3, 49 7, i I (method 5005) I 8, 9, 10, 11 I i I Groups C and D end-point i 1, 2, 7, 9 i I electrical parameters I I I (method 5005) I I *PDA applies to subgroup 1. Group A inspection. a. Tests shall be as specified in table I

34、I herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN and COUT measurements) shall be measured only for the initial test and d. Subgroups 7 and 8 shall consist of verifying the functionality of the device. after process or design changes which may

35、 affect input capacitance. A minimum sample size of five devices with zero rejects shall be required. form a part of the vendors test tape and shall be maintained and available from the approved sources of supply, These tests 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall

36、 be as specified in table II herein, b. Steady-state 1 ife test conditions, method 1005 of MIL-STD-883. (1) Test condition B or D using the circuit submitted with the certificate of compliance (see 3.6 herein). (2) TA = +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 10

37、05 of MIL-STD-883. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL -M-385 10. I REVISION LEVEL I SHEET I 17 DEFENSE ELECTRONICS SUPPLY CENTER DAYTON. OHIO 45444 I I 1 DESC FORM 193A t U. S. GOVERNMENT PRINTING OFFNE: 1W-549-904 SEP 87 Provided

38、by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-57b2-70708 59 W 7779976 OOOL27L b I STAN DARD I ZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON. OHIO 45444 6 NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for u

39、se when military specifications do not exist and qualified militar devices that will perform the required function are not available for OEM application. When a mifitary specification exists and the product covered by this drawing has been qualified for listing on QPL-38510, the device s ecified her

40、ein will be inactivated and will not be used for new design. The QPL-38510 product sial1 be the preferred item for all applications. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.3 Configura

41、tion control of SMDs. All proposed changes to existing SMDs will be coordinated with the users of record for the individual documents. accordance with MIL-STD-481 using DD Form 1693, Engineering Change Proposal (Short Form). Center when a system application requires configuration control and the app

42、licable SM). DESC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings, Users of drawings covering microelectronics devices (FSC 5962) should contact DESC-ECC, telephone (513) 296-6022. 6.5 Conunents. Comments on this drawing should

43、be directed to DESC-ECC, Dayton, Ohio 45444, or tel ephoTFE33 296-5375. 6.6 Terminal and pin definitions. . This coordination will be accomplished in 6.4 Record of users. Military and industrial users shall inform Defense Electronics Supply VDD, GND. The device operates from a single +5 Y supply. Al

44、l power and ground lines must be connected. SIZE A 5962-90708 REVISION LEVEL SHEET lA The 8-bit twos complement or unsigned magnitude X data input. X7 is the MSB and :k?kns the sign information for twos complement notation. The data on the X input is clocked into the input register on the rising edg

45、e of CLK X. Y7- . The 8-bit twos complement or unsigned magnitude Y data input. Y7 is the MSB and con?ains the sign information for twos complement notation. The data on the Y input is clocked into the input register on the rising edge of CLK Y. pia-9- P 1 8-0 is the accumulated product result. The

46、19-bit output is either the twos comp emen or unsigned magnitude result of the accumulated products, The output is divided into two 8-bit output words (MSP, LSP) and one 3-bit output word (XTP). P 8 is the MsB and contains the sign information for twos complement notation. Formats for twos complemen

47、t, fractional unsigned magnitude, integer twos complement and integer unsigned notation are shown on figure 4. CLK X, CLK Y. The rising edge of CLK X and CLK Y loads the data lines into the appropriate input register. The R?uND (RND), TWOS Complement (TC), Accumulate (ACC), and SUBtract (SUB) contro

48、l inputs are registered and loaded on the logical OR of both CLK X and CLK Y. Special attention to the clock signals is required if normally high clock signals are used. Problems can be avoided by the use of normally low clocks. CLK P. This input is used to clock the accumulated product sum into the output register. If ACCs high, the content of the output register is added to the next product generated and loaded into the output register. CLK P is also used to preload the output register from the output pins. I I -I ir U. C. GOVERNHEM PRIMING OFFICE 1PBB-549&W4 DESC FORM lg3A SEP 87 Provided