DLA SMD-5962-90754 REV B-2012 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASABLE ASYNCHRONOUS REGISTERED PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R218-92 ksr 92-06-09 William J. Johnson B Boilerplate update and part of five year review. lhl 12-02-01 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV B B B B B B B

2、B B SHEET 15 16 17 18 19 20 21 22 23 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth S. Rice, Jr. DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS A

3、VAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Charles Reusing APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS UV ERASABLE ASYNCHRONOUS REGISTERED PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON DRAWING APPROVAL DATE 90-05-24 AMSC N/A REVISION L

4、EVEL B SIZE A CAGE CODE 67268 5962-90754 SHEET 1 OF 23 DSCC FORM 2233 APR 97 5962-E124-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B

5、 SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Iden

6、tifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 90754 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator

7、Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, ap

8、pendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 CY7C331-40 Asynchronous Registered PL

9、D 40 ns 02 CY7C331-30 Asynchronous Registered PLD 30 ns 03 CY7C331-25 Asynchronous Registered PLD 25 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certi

10、fication to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter

11、 Descriptive designator Terminals Package style X See figure 1 28 Dual-in-line package 1/ Y GDFP2-F28 28 Flat pack style 1/ Z See figure 2 28 J-leaded chip carrier 1/ 3 CQCC1-N28 28 Square leadless chip carrier style 1/ 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device c

12、lasses Q and V or MIL-PRF-38535, appendix A for device class M. _ 1/ Lid shall be transparent to permit ultraviolet light erasure. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90754 DLA LAND AND MARITIME C

13、OLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ Supply voltage to ground potential . -0.5 V dc to +7.0 V dc DC voltage range applied to outputs in high Z state -0.5 V dc to +7.0 V dc DC input voltage . -3.0 V dc to +7.0 V dc Maximum power diss

14、ipation 3/ 1.2 W Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC): Case outlines Y and 3 See MIL-STD-1835 Case outline X 26C/W 4/ Case outline Z 20C/W 4/ Junction temperature (TJ) +175C Storage temperature range -65C to +150C Temperature under bias . -55C to +

15、125C 1.4 Recommended operating conditions. Supply voltage (VCC) +4.5 V dc to +5.5 V dc Ground voltage (GND) . 0 V dc Input high voltage (VIH) 2.2 V dc minimum Input low voltage (VIL) 0.8 V dc maximum Case operating temperature range (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specifica

16、tion, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-385

17、35 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Dra

18、wings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 2/ Stresses above the absolute maximum ra

19、ting may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ Must withstand the added PDdue to short circuit test (e.g., IOS). 4/ When the thermal resistance for this case is specified in MIL-STD-1835, that value shall sup

20、ersede the value indicated herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2.2 Order of precedence.

21、 In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements.

22、 The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The

23、 individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-3853

24、5 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figures 1 and 2. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 3. 3.2.3 Truth t

25、able. The truth table shall be as specified on figure 4. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 4. When required in screening (see 4.2 herein) or qualification conformance inspection, grou

26、ps A, C, or D (see 4.3), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of the total number of cells shall be programmed or at least 25 percent of the total number of cells to any altered item drawing. 3.2.3.2 Programmed devices. The truth table for progra

27、mmed devices shall be as specified by an attached altered item drawing. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and

28、shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.

29、2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall sti

30、ll be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in

31、MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this

32、drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an appro

33、ved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conforma

34、nce as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of ch

35、ange of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to r

36、eview the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90

37、754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). 3.11 Processing EPLDs. Al

38、l testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.11.1 Erasure of EPLDs. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.6. 3.11.2 Programmability of EPLDs. When spec

39、ified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.7. 3.11.3 Verification of erasure or programmed EPLDs. When specified, devices shall be verified as either programmed to the specified pattern or erased. As a minimum, verification sha

40、ll consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. Provided by IHSNot for ResaleNo reproduction or networking permitted w

41、ithout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device ty

42、pes Limits Unit unless otherwise specified Min Max Output high voltage VOHVCC= 4.5 V, IOH= -2.0 mA, VIN= VIH, VIL1, 2, 3 All 2.4 V Output low voltage VOLVCC= 4.5 V, IOL= 8.0 mA, VIN= VIH, VIL1, 2, 3 All 0.5 V Input high voltage 1/ VIH1, 2, 3 All 2.2 V Input low voltage 1/ VIL1, 2, 3 All 0.8 V Input

43、leakage current IIXVIN= 5.5 V to GND 1, 2, 3 All -10 10 A Output leakage current IOZVCC= 5.5 V VOUT= 5.5 V and GND 1, 2, 3 All -40 40 A Output short circuit Current 2/ 3/ IOSVCC= 5.5 V, VOUT= 0.5 V 1, 2, 3 All -30 -90 mA Power supply current at frequency 3/ ICC1VCC= 5.5 V, IOUT= 0 mA, VIN= GND, f =

44、fMAX51, 2, 3 All 200 mA Standby power supply current ICC2VCC= 5.5 V, IOUT= 0 mA, VIN= GND 1, 2, 3 All 150 mA Input capacitance 3/ CINVCC= 5.0 V TA= +25C, f = 1 MHz (see 4.4.1c) 4 All 7 pF Output capacitance 3/ COUTVCC= 5.0 V TA= +25C, f = 1 MHz (see 4.4.1c) 4 All 8 pF Functional tests See 4.4.1d 7,

45、8 All Input or feedback to Propagation delay 5/ tPD4/ 9, 10, 11 01 3 40 ns 02 3 30 03 4.6 25 Input register clock to output delay 6/ tICO9, 10, 11 01 65 ns 02 50 03 45 Output data stable time from input clock 6/ tIOH9, 10, 11 All 5 ns Input or feedback setup time to input register clock 6/ tIS9, 10,

46、 11 All 5 ns Input register hold time from input clock 6/ tIH9, 10, 11 01 20 ns 02 15 03 13 Input to input register asynchronous reset delay 6/ tIAR9, 10, 11 01 65 ns 02 50 03 45 Input register reset width 3/ 6/ tIRW9, 10, 11 01 65 ns 02 50 03 45 See footnotes at end of table. Provided by IHSNot for

47、 ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditio

48、ns 4/ -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device types Limits Unit unless otherwise specified Min Max Input register reset recovery time 3/ 6/ tIRR9, 10, 11 01 65 ns 02 50 03 45 Input to input register asynchronous set delay 6/ tIAS9, 10, 11 01 65 ns 02 50 03 45 Input register set width 3/ 6/ tISW9, 10, 11 01 65 ns 02 50 03 45 Input register set recovery time 3/ 6/ tISR9, 10, 11 01 65 ns 02 50 03 45 Input and output clock width high 3/ 6/ 7/ 8/ tWH9, 10,