DLA SMD-5962-90758 REV B-2012 MICROCIRCUIT DIGITAL HIGH SPEED CMOS DUAL 2-BIT BISTABLE TRANSPARENT LATCH TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Redraw the switching waveforms and add notes to figure 4, switching waveforms and test circuit. Update boilerplate to MIL-PRF-38535 requirements. Editorial changes throughout. LTG 06-02-23 Thomas M. Hess B Update test condition of high and low le

2、vel output voltage (VOHand VOL) to table I. Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 12-07-25 Thomas M. Hess REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Marcia B. Kelleher DLA LAND AN

3、D MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Thomas J. Riccuiti APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, , HIGH SPEED C

4、MOS, DUAL 2-BIT BISTABLE TRANSPARENT LATCH, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 91-04-24 REVISION LEVEL B SIZE A CAGE CODE 67268 5962-90758 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E374-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without licens

5、e from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90758 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and spac

6、e application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5

7、962 - 90758 01 M E A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specif

8、ied RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify th

9、e circuit function as follows: Device type Generic number Circuit function 01 54HCT75 Dual 2-bit bistable transparent latch, TTL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device req

10、uirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in

11、MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for R

12、esaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90758 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5 V dc to +7.0

13、 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Clamp diode current 20 mA DC output current (per pin) 25 mA DC VCCor GND current (per pin) . 50 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD)

14、 . 500 Mw 4/ Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. 3/ Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Input voltage range (VIN) 0.0 V dc to VCCOutput voltage

15、range (VOUT) 0.0 V dc to VCCCase operating temperature range (TC) . -55C to +125C Input rise or fall time (tr, tf): VCC= 4.5 V, 5.5 V 0 to 500 ns Minimum setup time, mDn to enable (ts): TC= +25C, VCC= 4.5 V . 12ns TC= -55C to +125C, VCC= 4.5 V . 18 ns Minimum pulse width, enable input (tw): TC= +25C

16、, VCC= 4.5 V . 16 ns TC= -55C to +125C, VCC= 4.5 V . 24 ns Minimum hold time, enable to mDn (th): TC= +25C, VCC= 4.5 V . 3 ns TC= -55C to +125C, VCC= 4.5 V . 3 ns 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks for

17、m a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE

18、 STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are avai

19、lable online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may de

20、grade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ For TC= +100C to +125C, derate linearly at 12

21、 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90758 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following docum

22、ent(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Adva

23、nced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the

24、 references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall b

25、e in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance

26、 with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A an

27、d herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The log

28、ic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical per

29、formance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each sub

30、group are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marki

31、ng the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance ma

32、rk. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be

33、required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The

34、 certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MI

35、L-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of

36、change for device class M. For device class M, notification to DLA Land and Maritime -VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DLA Land

37、 and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device cl

38、ass M. Device class M devices covered by this drawing shall be in microcircuit group number 38 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90758 DLA LAND AND MARITIME COLU

39、MBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max High level output voltage VOHVCC= 4.5 V VIN= VIH= 2.0 V or V

40、IL= 0.8 V IOH= -20 A 1, 2, 3 All 4.4 V IOH= -4.0 mA 3.7 Low level output voltage VOLVCC= 4.5 V VIN= VIH= 2.0 V or VIL= 0.8 V IOL= +20 A 1, 2, 3 All 0.1 V IOL= +4.0 mA 0.4 High level input voltage VIHVCC= 4.5 V 2/ 1, 2, 3 All 2.0 V Low level input voltage VILVCC= 4.5 V 2/ 1, 2, 3 All 0.8 V Quiescent

41、supply current ICCVCC= 5.5 V, VIN= VCCor GND IOUT= 0.0 A 1, 2, 3 All 80 A Input leakage current IINVCC= 5.5 V, VIN= VCCor GND 1, 2, 3 All 1.0 A Additional quiescent supply current, TTL inputs ICCAny one input VIN= 2.4 V or 0.5 V Other inputs VIN= VCCor GND VCC= 5.5 V 1, 2, 3 All 3.0 mA Input capacit

42、ance CINVIN= 0 V, see 4.4.1c 4 All 10 pF Power dissipation capacitance 3/ CPDSee 4.4.1c 4 All 58 pF Functional tests See 4.4.1b 7, 8 All Propagation delay time, mDn to mQn tPHL1, tPLH1VCC= 4.5 V CL= 50 pF See figure 4 9 All 28 ns 10, 11 42 Propagation delay time, mDn to mQn tPHL2, tPLH29 All 28 ns 1

43、0, 11 42 Propagation delay time, mE to mQn tPHL3, tPLH3 9 All 28 ns 10, 11 42 Propagation delay time, mE to mQn tPHL4, tPLH49 All 30 ns 10, 11 45 Transition time 4/ tTHL, tTLH9 All 15 ns 10, 11 22 1/ For a power supply of 5.0 V 10%, the worst case output voltages (VOHand VOL) occur for HCT at VCC= 4

44、.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst cases VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. 2/ Tests are not required if applied as a forcing function for VOHor VOLtests. 3/ Power dissipation capacitance (CPD) determines the dynamic power consumpti

45、on (PD) and the dynamic current consumption (IS): PD(total) = (CPD+ CL) VCC2f + (VCCx ICC) + (n x d x ICCx VCC) IS= (CPD+ CL) VCC f + ICC+ (n x d x ICC) f is input switching frequency; n is number of inputs switching; d is duty cycle; CLis load capacitance on each output. 4/ This parameter, if not t

46、ested, shall be guaranteed to the limits specified in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90758 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR

47、 97 Device type All Case outline E Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1Q0 1D0 1D1 2E VCC2D0 2D1 2Q1 2Q1 2Q0 2Q0 GND 1E 1Q1 1Q1 1Q0 FIGURE 1. Terminal connections. Inputs Outputs mDn mE mQn mQn L H L H H H H L L L Q0 Q0 H = High voltage level L = Low voltage level

48、Q0 = The level of Q before the transition of E. Q0 = The level of Q before the transition of E. FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90758 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90758 DLA LAND