DLA SMD-5962-90803 REV D-2012 MICROCIRCUIT MEMORY DIGITAL CMOS 8K X 8-BIT PROM MONOLITHIC SILICON.pdf

1、REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to reflect current requirements. Editorial changes throughout. - gap 01-02-15 Raymond Monnin B Boilerplate update and part of five year review. tcr 07-01-29 Joseph Rodenbeck C Correction to Table I; ICC2 remove devices 05-07 and 08

2、from the device type column. ksr 07-06-11 Robert M. Heber D Sheet 10, FIGURE 4, Output Load Circuit values, change R1value for device types 4 and 8 from 658 ohms to 250 ohms, and R2from 403 ohms to 167 ohms. Boilerplate changes as needed. - glg 12-03-14 Charles Saffle THE ORIGINAL FIRST PAGE OF THIS

3、 DRAWING HAS BEEN REPLACED. REV SHEET REV D SHEET 15 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-3990 http:/www.l

4、andandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS 8K X 8-BIT PROM, MONOLITHIC SILICON DRAWING APPROVAL DATE 92-07-20 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 59

5、62-90803 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E091-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90803 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1

6、. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When avail

7、able, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 90803 01 M X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead f

8、inish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels a

9、nd are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 7C261 8K X 8-bit PROM 55 ns 02 7C261 8K X 8-bit PROM 45 ns 03 7C261

10、8K X 8-bit PROM 35 ns 04 7C261 8K X 8-bit PROM 25 ns 05 7C263, 7C264 8K X 8-bit PROM 55 ns 06 7C263, 7C264 8K X 8-bit PROM 45 ns 07 7C263, 7C264 8K X 8-bit PROM 35 ns 08 7C263, 7C264 8K X 8-bit PROM 25 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the p

11、roduct assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4

12、Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style J GDIP1-T24 or CDIP2-T24 24 Dual-in-line K GDFP2-F24 or CDFP3-F24 24 Flat pack L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 3 CQCC1-N28 28 Square leadless chip

13、 carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90803 D

14、LA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range to ground potential (VCC) -0.5 V dc to +7.0 V dc DC voltage applied to the outputs in the high-Z state . -0.5 V dc to +7.0 V dc DC input voltage . -3.0

15、V dc to +7.0 V dc DC program voltage 13.0 V dc Maximum power dissipation . 1.0 W 2/ Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) +175C Storage temperature range (TSTG) -65C to +150C 1.4 Recommended operating condi

16、tions. Supply voltage (VCC) . +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) 0 V dc Input high voltage (VIH) . 2.0 V dc minimum Input low voltage (VIL) . 0.8 V dc maximum 3/ Case operating temperature range (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standar

17、ds, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrat

18、ed Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HD

19、BK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absolute maximum rating may caus

20、e permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Must withstand the added PDdue to short circuit test; e.g., IOS. 3/ VILnegative undershoots to a minimum of -3.0 V dc are allowed for pulse widths VIH1, 2, 3 01-03 30 mA IOUT

21、= 0 mA 04 50 Input capacitance 3/ CINVCC= 5.0 V, VIN= 0 V 4 All 10 pF TA= +25C, f = 1 MHz (see 4.4.1d) Output capacitance 3/ COUTVCC= 5.0 V, VOUT= 0 V 4 All 10 pF TA= +25C, f = 1 MHz (see 4.4.1d) Functional tests See 4.4.1c 7, 8 All Address to output valid tAASee figures 3 and 4 and 9, 10, 11 01, 05

22、 55 ns note 5/ 02, 06 45 03, 07 35 04, 08 25 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90803 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC

23、FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Chip select active to tACSSee figures 3 and 4 and 9, 10, 11 01 55 ns output valid note 5/ 02 4

24、5 03 40 04 25 05 35 06 30 07 20 08 15 Chip select active to tPU9, 10, 11 01-04 0 ns power-up 3/ Chip select inactive to tPD9, 10, 11 01 55 ns power-down 3/ 02 45 03 35 04 25 Chip select inactive tHZCSSee figures 3 and 4 and 9, 10, 11 01 55 ns to high-Z 3/ note 5/ and 6/ 02 45 03, 05 35 04, 07 25 06

25、30 08 15 1/ These are absolute values with respect to device ground and all overshoots and undershoots due to system or tester noise are included. 2/ For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 3/ Tested initially

26、 and after any design or process changes that affect that parameter, and therefore shall be guaranteed to the limits specified in table I. 4/ At f = fmax, address inputs are cycling at the maximum frequency of 1/tAA. 5/ AC tests are performed with input rise and fall times of 5 ns or less, timing re

27、ference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and the output load in figure 4. 6/ Transition is measured at steady state high level -500 mV or steady state low level +500 mV on the output from the 1.5 V level on the input, CL= 5 pF (including scope and jig). See figure 4. Provided by IH

28、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90803 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 Device types All Case outlines J, K, and L 3 Terminal number Terminal sym

29、bol 1 A7NC 2 A6A73 A5A64 A4A55 A3A46 A2A37 A1A28 A0A19 O0A010 O1NC 11 O2O012 GND O113 O3O214 O4GND 15 O5NC 16 O6O317 O7O418 A12O519 A11O620 CS O721 A10NC 22 A9A1223 A8A1124 VCCCS 25 - A1026 - A927 - A828 - VCCNC = no connection FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduc

30、tion or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90803 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 9 DSCC FORM 2234 APR 97 Type Mode Outputs A12A11CS A10A9A8VCCPower All Read DOUTA12A11VILA10A9A8VCCICC01-04 Not selected Hi

31、gh-Z A12A11VIHA10A9A8VCCISB05-08 Not selected High-Z A12A11VIHA10A9A8VCCICCAll Program 1/ DINVILPVPPVILPLatch VILPVIHPVCCPICCAll Program High-Z VILPVPPVILPLatch VIHPVIHPVCCICCinhibit 1/ All Program DOUTVILPVPPVILPLatch VIHPVILPVCCICCverify 1/ All Blank check 1/ DOUTVILPVPPVILPLatch VIHPVILPVCCICC1/

32、See 4.5. FIGURE 2. Truth table. FIGURE 3. Switching waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90803 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 10 DSCC FORM 2234 AP

33、R 97 Circuit A Circuit B Output load Output load for tHZCSNOTE: Including scope and jig. (minimum values) Load All device types R1 250 R2 167 AC test conditions Input pulse levels GND to 3.0 V Input rise and fall times 5 ns Input timing reference levels 1.5 V Output reference levels 1.5 V FIGURE 4.

34、Output load circuit and test conditions. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90803 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 11 DSCC FORM 2234 APR 97 4. VERIFICATION 4

35、.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herei

36、n. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance ins

37、pection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition D. The test circ

38、uit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified

39、 in method 1015. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table IIA herein. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified

40、in the device manufacturers QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparin

41、g activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional s

42、creening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performe

43、d shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as

44、 specified herein. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspection

45、s (see 4.4.1 through 4.4.4). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90803 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 12 DSCC FORM 2234 APR 97 4.4.1 Group A inspection. a.

46、Tests shall be as specified in table IIA herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V, subgroups 7 and 8 shall include verifying the funct

47、ionality of the device. d. Subgroup 4 (CINand COUTmeasurements) shall be measured only for the initial test and after process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is

48、15 devices with no failures, and all input and output terminals tested. e. Unprogrammed devices shall be tested for programmability and ac performance compliance to the requirements of group A, subgroups 9, 10, and 11. Either of two techniques is acceptable: (1) Testing the entire lot using additional built-in test circuitry which allows the manufacturer to verify programmability and ac performance without programming the user array. I