DLA SMD-5962-90845 REV B-2003 MICROCIRCUIT LINEAR 8-BIT A D PERIPHERAL WITH SERIAL CONTROL MONOLITHIC SILICON《硅单块 带串控制的8比特模拟数字边缘的直线式微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R222-92. 92-06-19 M. A. FRYE B Correction made to the title block on sheet 1. Drawing updated to reflect current requirements. -rrp 03-03-03 R. MONNIN THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED.

2、 REV SHET REV SHET REV STATUS REV B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Rick C. Officer DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles E. Besore COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILAB

3、LE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, 8-BIT A/D PERIPHERAL WITH SERIAL CONTROL, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 91-04-29 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-90845 SHEET 1 OF 13 DSCC FORM 22

4、33 APR 97 5962-E260-03 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90845 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 4321

5、6-5000 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflec

6、ted in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 90845 01 Q P X Federal stock class designator RHA designator (see 1.2.1) Devicetype (see 1.2.2) D

7、evice class designator Caseoutline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet

8、 the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Input/output clock frequency 0

9、1 TLC548M 8-bit analog-to-digital 2.048 MHz peripheral with serial control 02 TLC549M 8-bit analog-to-digital 1.1 MHz peripheral with serial control 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device r

10、equirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated i

11、n MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style P GDIP1-T8 or CDIP2-T8 8 Dual-in-line 2 CQCC1-N20 20 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A f

12、or device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90845 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1

13、/ Supply voltage (VCC) . +6.5 V 2/ Input voltage range at any input -0.3 V to VCC+ 0.3 V Output voltage range . -0.3 V to VCC+ 0.3 V Peak input current range (any input) . 10 mA Peak total input current range (all inputs) . 30 mA Storage temperature range . -65C to +150C Case temperature for 60 seco

14、nds, case 2 +260C Lead temperature soldering, 1.6 mm (0.0625) from case for 60 seconds: Case P . +300C Power dissipation (PD), (TA +25C): 3/ Case P . 1050 mW Case 2 . 1375 mW Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA): Case P . 110C/W Case

15、 2 . 1375C/W Junction temperature (TJ) . +150C 1.4 Recommended operating conditions. Supply voltage (VCC) . 4 V minimum, 6 V maximum Positive reference voltage (VREF+) 2.5 V minimum, VCC+ 0.1 V maximum 4/ Negative reference voltage (VREF-) . -0.1 V minimum, 2.5 V maximum 4/ Differential reference vo

16、ltage (VREF+), (VREF-) 1 V minimum, VCC+ 0.2 V maximum 4/ Analog input voltage 0 V minimum, VCCmaximum 4/ High level control input voltage (VIH) . 2 V minimum 5/ Low level control input voltage (VIL) 0.8 V maximum 5/ Input/output clock frequency fCLK(I/O): 5/ Device type 01 . 0 MHz minimum, 2.048 MH

17、z maximum Device type 02 . 0 MHz minimum, 1.1 MHz maximum Input/output clock high tWH(I/O): 5/ Device type 01 . 200 ns minimum Device type 02 . 404 ns minimum Input/output clock low tWL(I/O): 5/ Device type 01 . 200 ns minimum Device type 02 . 404 ns minimum Duration of CS input high state during co

18、nversion tWH(CS)17 s minimum 4/ 5/ Setup time, CS low before first I/O clock tSU(CS)1.4 s minimum 5/ 6/ Ambient operating free-air temperature (TA) . -55C to +125C 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may deg

19、rade performance and affect reliability. 2/ All voltage values are with respect to network ground terminal with the REF- and GND terminal connected together. 3/ Derate 8.4 mW/C above TA= +25C for case P and derate 11.0 mW/C above TA= +25C for case 2. 4/ Analog input voltages greater than that applie

20、d to REF+ convert to all ones (11111111), while input voltages less than that applied to REF- convert to all zeros (00000000). For proper operation, the positive reference voltage VREF+must be at least 1 V greater than the negative voltage VREF-. In addition, unadjusted errors may increase as the di

21、fferential reference voltage VREF+- VREF-falls below 4.75 V. 5/ VCC= 4.75 V to 5.5 V 6/ To minimize errors caused by noise at the CS input, the internal circuitry waits for two rising edges and one falling edge of internal system clock after CS falling edge before responding to control input signals

22、. This CS setup time is given by the tENand tSU(CS)specifications. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90845 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 4 DSCC

23、FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue o

24、f the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method S

25、tandard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and

26、handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothin

27、g in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified i

28、n the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as

29、 specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s)

30、shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirr

31、adiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.

32、5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the

33、 “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reprodu

34、ction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90845 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TA +125C unl

35、ess otherwise specified Group A subgroups Device type Limits Unit Min Max High level output voltage VOHVCC= 4.75 V, IOH= -360 A 1, 2, 3 All 2.4 V Low level output voltage VOLVCC= 4.75 V, IOL= 3.2 mA 1, 2, 3 All 0.4 V VO= VCC, VCC= 5.5 V, CS at VCC10 Off state (high impedance state) output current IO

36、ZVO= 0, VCC= 5.5 V, CS at VCC1, 2, 3 All -10 A High level input current, control inputs IIHVI= VCC= 5.5 V 1, 2, 3 All 2.5 A Low level input current, control inputs IILVI= 0, VCC= 5.5 V 1, 2, 3 All -2.5 A Analog input at VCC, VCC= 5.5 V 1 Analog channel “ON” state input current, during sample cycle I

37、I(ON)Analog input at 0 V, VCC= 5.5 V 1, 2, 3 All -1 A Operating supply current ICCVCC= 5.5 V, CS at 0 V 1, 2, 3 All 3 mA Supply and reference current ICC+IREFVREF+= VCC= 5.5 V 1, 2, 3 All 3.25 mA Linearity error 1/ EL1, 2, 3 All 0.5 LSB Zero error 2/ E01, 2, 3 All 0.5 LSB Full scale error 2/ EFS1, 2

38、, 3 All 0.5 LSB Total unadjusted error 3/ EU1, 2, 3 All 0.5 LSB Analog inputs, see 4.4.1c 55 Input capacitance CINControl inputs, see 4.4.1c 4 All 15 pF Conversion time tCONVSee figure 2 9, 10, 11 All 17 s 01 22 Total access and conversion time tACSee figure 2 9, 10, 11 02 25 s Channel acquisition t

39、ime (sample cycle) tACQSee figure 2 9, 10, 11 All 4 I/O clock cycle Time output data remains valid after I/O clock falling edge tVVCC= 5.0 V 9, 10, 11 All 10 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD M

40、ICROCIRCUIT DRAWING SIZE A 5962-90845 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions -55C TA +125C unless otherwise specified Group A subgroups Device type Limit

41、s Unit Min Max 01 300 Delay time to data output valid tDI/O clock falling edge, VCC= 5.0 V 9, 10, 11 02 400 ns Output enable time tENVCC= 5.0 V, See figures 2 and 3 9, 10, 11 All 1.4 s Output disable time tDISVCC= 5.0 V, See figures 2 and 3 9, 01, 11 All 150 ns Data bus rise time tR(bus)VCC= 5.0 V,

42、See figures 2 and 3 9, 10, 11 All 300 ns Data bus fall time tF(bus)VCC= 5.0 V, See figures 2 and 3 9, 10, 11 All 300 ns 1/ Linearity error is the deviation from the best straight line through the A/D transfer characteristics. 2/ Zero error is the difference between 00000000 and the converted output

43、for zero input voltage; full scale error is the difference between 11111111 and the converted output for full scale input voltage. 3/ Total unadjusted error is the sum of linearity, zero, and full scale errors. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V sh

44、all be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order t

45、o supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to

46、 listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A cer

47、tificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of

48、 change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the