DLA SMD-5962-90869 REV C-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 64K x 8 ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM) MONOLITHIC SILICON《硅单块 互补金属氧化物半导体64K X 8电压消除式可程序.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R114-92. glg 92-01-22 Michael A. Frye B Changes in accordance with NOR 5962-R160-98. glg 98-08-06 Raymond Monnin C Boilerplate update and part of five year review. tcr 07-04-13 Robert M. Heber THE ORIGINAL FIRS

2、T PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV C C C C C C C C C C C C C C C C C C C C SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPL

3、Y CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS 64K x 8 ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY

4、 (EEPROM), MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 91-10-18 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-90869 SHEET 1 OF 34 DSCC FORM 2233 APR 97 5962-E079-07 Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro

5、m IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90869 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and

6、space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following examp

7、le: 5962 - 90869 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 spe

8、cified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify

9、 the circuit function as follows: Device type Generic number Circuit function Access time Write speed Write mode Endurance 01 28C512 64K x 8 EEPROM 250 ns 10 ms Byte/Page 10,000 cycle 02 “ 64K x 8 EEPROM 250 ns 5 ms Byte/Page 10,000 cycle 03 “ 64K x 8 EEPROM 200 ns 10 ms Byte/Page 10,000 cycle 04 “

10、64K x 8 EEPROM 200 ns 5 ms Byte/Page 10,000 cycle 05 “ 64K x 8 EEPROM 150 ns 10 ms Byte/Page 10,000 cycle 06 “ 64K x 8 EEPROM 150 ns 5 ms Byte/Page 10,000 cycle 07 “ 64K x 8 EEPROM 120 ns 10 ms Byte/Page 10,000 cycle 08 “ 64K x 8 EEPROM 120 ns 5 ms Byte/Page 10,000 cycle 09 28C513 64K x 8 EEPROM 250

11、 ns 10 ms Byte/Page 10,000 cycle 10 “ 64K x 8 EEPROM 250 ns 5 ms Byte/Page 10,000 cycle 11 “ 64K x 8 EEPROM 200 ns 10 ms Byte/Page 10,000 cycle 12 “ 64K x 8 EEPROM 200 ns 5 ms Byte/Page 10,000 cycle 13 “ 64K x 8 EEPROM 150 ns 10 ms Byte/Page 10,000 cycle 14 “ 64K x 8 EEPROM 150 ns 5 ms Byte/Page 10,

12、000 cycle 15 “ 64K x 8 EEPROM 120 ns 10 ms Byte/Page 10,000 cycle 16 “ 64K x 8 EEPROM 120 ns 5 ms Byte/Page 10,000 cycle 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M

13、Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

14、IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90869 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals

15、 Package style X See figure 1 (1.685“ x .600“ x .225“) 32 dual in-line package Y C-12 (.560“ x .458“ x .120“) 32 rectangular chip carrier package Z See figure 1 (.830“ x .416“ x .120“) 32 flat package U See figure 1 (.760“ x .760“ x .120“ 36 pin grid array 1.2.5 Lead finish. The lead finish is as sp

16、ecified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) . -0.5 V dc to +6.0 V dc 3/ Operating case temperature range -55C to +125C Storage temperature range. -65C to +150C Lead temperature (so

17、ldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC): Case X 28C/W 4/ Case Y . See MIL-STD-1835 Case Z . 22C/W 4/ Case U . 20C/W 4/ Maximum power dissipation (PD) 1.0 watts Junction temperature (TJ) +175C 5/ Endurance. 10,000 cycles/byte (minimum) Data retention . 10 years minimum

18、1.4 Recommended operating conditions. Supply voltage range (VCC) . 4.5 V dc minimum to 5.5 V dc maximum Supply voltage (VSS) 0.0 V dc High level input voltage range (VIH) 2.0 V dc to VCC+ 1.0 V dc Low level input voltage range (VIL). -0.1 V dc to 0.8 V dc Case operating temperature range (TC) . -55C

19、 to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or

20、 contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliabil

21、ity. 2/ All voltages referenced to VSS(VSS= ground), unless otherwise specified. 3/ Negative undershoots to a minimum of -1.0 V are allowed with a maximum of 20 ns pulse width. 4/ When the thermal resistance for this case is specified in MIL-STD-1835, that value shall supersede the value indicated h

22、erein. 5/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING

23、 SIZE A 5962-90869 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HAN

24、DBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Bui

25、lding 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR TESTIN

26、G AND MATERIALS (ASTM) ASTM Standard F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, Wes

27、t Conshohocken, PA 19428-2959; http:/www.astm.org.) ELECTRONICS INDUSTRIES ALLIANCE (EIA) JEDEC Standard EIA/JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Governm

28、ent standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this dr

29、awing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q

30、and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall

31、be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-3853

32、5, appendix A and herein for device class M. 3.2.1 Case outlines. The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. The truth table shall be as specified on figure 3. 3

33、.2.4 Radiation exposure circuit. The radiation exposure circuit shall be as specified in 4.4.5e. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as

34、specified in table IA and shall apply over the full case operating temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90869 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LE

35、VEL C SHEET 5 DSCC FORM 2234 APR 97 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition,

36、the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking f

37、or device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The comp

38、liance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 here

39、in). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing sh

40、all affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and

41、 V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquir

42、ed to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentat

43、ion shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). 3.11 Processing of EEPROMs: All testing requirements and

44、quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.11.1 Conditions of the supplied devices: Devices will be supplied in cleared state (logic “1s“). No provision will be made for supplying written devices. 3.11.2 Clearing of EEPROMs: When specified, device

45、s shall be cleared in accordance with the procedures and characteristics specified in 4.6.4. 3.11.3 Writing of EEPROMs: When specified, devices shall be written in accordance with the procedures and characteristics specified in 4.6.3. 3.11.4 Verification of state of EEPROMs: When specified, devices

46、shall be verified as either written to the specified pattern or cleared. As a minimum, verification shall consist of performing a read of the entire array to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure and the

47、 device shall be removed from the lot or sample. 3.11.5 Power supply sequence of EEPROMs: In order to reduce the probability of inadvertent writes, the following power supply sequences shall be observed: a. A logic high state shall be applied to WE and/or CE at the same time or before the applicatio

48、n of VCC. b. A logic high state shall be applied to WE and/or CE at the same time or before the removal of VCC. 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accorda