DLA SMD-5962-90908 REV A-2003 MICROCIRCUIT LINEAR CMOS 8-BIT DAC WITH OUTPUT AMPLIFIER MONOLITHIC SILICON《硅单块 带输出放大器的互补金属氧化物半导体8比特数字至模拟转换器 直线式微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. - ro 03-01-28 R. MONNIN REV SHET REV SHET REV STATUS REV A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY SANDRA ROONEY DEFENSE SUPPLY CENTER COLUMBUS STANDAR

2、D MICROCIRCUIT DRAWING CHECKED BY SANDRA ROONEY COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY MICHAEL A. FRYE MICROCIRCUIT, LINEAR, CMOS 8-BIT DAC WITH OUTPUT AMPLIFIER, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWIN

3、G APPROVAL DATE 94-04-29 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-90908 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E186-03 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license

4、from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90908 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) a

5、nd space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following ex

6、ample: 5962 - 90908 01 M V X Federal stock class designator RHA designator (see 1.2.1) Devicetype (see 1.2.2) Device class designator Caseoutline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535

7、specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) ident

8、ify the circuit function as follows: Device type Generic number Circuit function 01 AD7224U 8-bit DAC with output amplifier 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation

9、 M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as fol

10、lows: Outline letter Descriptive designator Terminals Package style V GDIP1-T18 or CDIP2-T18 18 Dual-in-line 2 CQCC1-N20 20 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Pro

11、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90908 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ VDDto AGND -0.3 V dc

12、, +17 V dc VDDto DGND -0.3 V dc, +17 V dc VSSto AGND . -7 V dc, VDDVSSto DGND . -7 V dc, VDDVDDto VSS. -0.3 V dc, +24 V dc AGND to DGND -0.3 V dc, VDDDigital input voltage to DGND -0.3 V dc, VDDVREFto AGND . -0.3 V dc, VDDVOUTto AGND . VSS, VDDPower dissipation (PD) 450 mW 2/ Storage temperature ran

13、ge . -65C to +160C Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA): Case outline V 120C/W Case outline 2 120C/W 1.4 Recommended operating conditions. Operating temperature range . -55C to +125C 2.

14、APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of

15、Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuit

16、s. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are availa

17、ble from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Derat

18、e linearly above TA= +75C at 6 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90908 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2.2 Order of

19、precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item re

20、quirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described

21、herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in M

22、IL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. T

23、he truth table shall be as specified on figure 2. 3.2.4 Timing waveforms. The timing waveforms shall be as specified on figure 3. 3.3 Electrical performance characteristics and post irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post i

24、rradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3

25、.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking th

26、e “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. T

27、he certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be requi

28、red from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The cert

29、ificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix

30、A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device clas

31、s M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiri

32、ng activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall

33、be in microcircuit group number 80 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90908 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 5 DSCC

34、 FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Resolution RES 1,2,3 01 8 Bits Relative accuracy RA VDD= +14 V, VSS= -5 V, 1 01 1 LSB VREF= +10 V 2,3 0.5 Total unad

35、justed error ETVDD= +14 V, VSS= -5 V, 1 01 2 LSB VREF= +10 V 2,3 1 Differential nonlinearity DNL Guaranteed monotonic to 8 bits 1,2,3 01 1 LSB Full scale error AEVDD= +14 V, VSS= -5 V, 1 01 1.5 LSB VREF= +10 V 2,3 1.0 Zero code error AZCEVDD= +16.5 V, 11.4 V and 14 V, 1 01 30 mV VSS= -5 V, VREF= VDD

36、 4 V 2,3 20 Full scale temp 2/ coefficient dAE/ dTVDD= 14 V to 16.5 V, VREF= +10 V 1,2,3 01 20 ppm/C Reference input resistance RINVDD= 14 V 1,2,3 01 8 k Voltage output slew rate tSR4 01 2.5 V/s Reference input capacitance CINOccurs when DAC is loaded with all 1s 4 01 100 pF Digital input leakage cu

37、rrent IINVIN= 0 V or VDD, VDD= 16.8 V 1,2,3 01 1 A Digital input high voltage VIHVDD= 11.4 V, VREF= VDD 4 V 7,8 01 2.4 V Digital input low voltage VILVDD= 11.4 V, VREF= VDD 4 V 7,8 01 0.8 V See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without li

38、cense from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90908 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Gro

39、up A subgroups Device type Limits Unit Min Max Positive power supply current IDDOutput unloaded: VIN= VILor VIH, 1 01 4 mA VDD= 16.5 V, VSS= -5.5 V, VREF= 12.5 V 2,3 6 Negative power supply current ISSOutput unloaded: VIN= VILor VIH, 1 01 3 mA VDD= 16.5 V, VSS= -5.5 V, VREF= 12.5 V 2,3 5 Voltage out

40、put settling time tSL2/ 3/ positive full-scale change 9,10,11 01 5 s Chip select / load DAC pulse width tLD2/ 9,10,11 01 200 ns Write / reset pulse width tWR2/ 9,10,11 01 200 ns Chip select / load DAC to write setup time tCS2/ 9,10,11 01 0 ns Chip select / load DAC to write hold time tCH2/ 9,10,11 0

41、1 0 ns Data valid to write setup time tDS2/ 9,10,11 01 100 ns Data valid to write hold time tDH2/ 9,10,11 01 10 ns 1/ VDD= +11.4 V to 16.5 V; VSS= -5 V 10%; AGND= DGND= 0 V; VREF= +2 V to (VDO 4 V) unless otherwise specified. 2/ Guaranteed, if not tested, to the limits specified in table I herein. 3

42、/ VREF= +10 V; settling time to 0.5 LSB. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90908 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 Device ty

43、pe 01 Case outlines V 2 Terminal number Terminal symbol 1 VSSNC 2 VOUTVSS3 VREFVOUT4 AGND VREF5 DGND AGND 6 DB7 (MSB) DGND 7 DB6 DB7 (MSB) 8 DB5 DB6 9 DB4 DB5 10 DB3 DB4 11 DB2 NC 12 DB1 DB3 13 DB0 (LSB) DB2 14 CS DB1 15 WR DB0 (LSB) 16 LDAC CS 17 RESET WR 18 VDDLDAC 19 - RESET 20 - VDDNC = No conne

44、ction FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90908 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 RESET LDAC W

45、R CS Function H L L L Both registers are transparent H X H X Both registers are latched H H X H Both registers are latched H H L L Input register transparent H H L Input register latched H L L H DAC register transparent H L H DAC register latched L X X X Both registers loaded with all zeros H H H Bo

46、th registers latched with all zeros and output remains at zero L L L Both registers are transparent and output follows input data H = High state, L = Low state, X = Dont care FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STAN

47、DARD MICROCIRCUIT DRAWING SIZE A 5962-90908 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 9 DSCC FORM 2234 APR 97 NOTES: 1. All input signal rise and fall times measured from 10 % to 90 % of VDD. tr= tf= 20 ns over VDDrange. 2. Timing measurement reference level is

48、: ( VINH+ VINL) / 2. FIGURE 3. Timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90908 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 10 DSCC FORM 2234 APR 97 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturers Quality Manage