DLA SMD-5962-91618 REV A-2013 MICROCIRCUIT MEMORY DIGITAL CMOS 2K X 9 PARALLEL FIFO MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Updated boilerplate to reflect current requirements. - glg 13-01-28 Charles Saffle THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV A A A A A SHEET 15 16 17 18 19 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6

2、 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles Reusing COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Monica L. Poelking MICROCIRCUIT, MEMORY,

3、 DIGITAL, CMOS, 2K X 9 FIFO, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 27 March 1990 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-91618 SHEET 1 OF 19 DSCC FORM 2233 APR 97 5962-E219-13 Provided by IHSNot for ResaleNo reproduction or networking permit

4、ted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91618 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuit

5、s in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN shall be as shown in the following example: 5962-91618 01 X A | | | | | | | | | | | | Drawing number Device type Case outline Lead finish (see 1.2.1) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). T

6、he device type(s) identify the circuit function as follows: Device type Generic number Circuit Access time 01 72031 2K X 9-bit parallel FIFO with OE 50 ns 02 72031 2K X 9-bit parallel FIFO with OE 40 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835, and as follows: Out

7、line letter Descriptive designator Terminals Package style X GDIP1-T32 or CDIP2-T32 32 dual-in-line package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Terminal voltage with respect to ground . -0.5 V dc to +7.0 V dc DC output cur

8、rent . 50 mA Storage temperature range -65C to +150C Maximum power dissipation (PD): . 1.0 W Lead temperature (soldering, 10 seconds) . +260C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) . +150C 2/ 1.4 Recommended operating conditions. Supply voltage range (VC

9、C). +4.5 V dc to +5.5 V dc Minimum high level input voltage (VIH) . 2.2 V dc Maximum low level input voltage (VIL) . +0.8 V dc Case operating temperature range (TC) . -55C to +125C 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maxim

10、um levels may degrade performance and affect reliability. 2/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted without

11、 license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91618 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks f

12、orm a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFEN

13、SE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are av

14、ailable online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwis

15、e specified, the issues of the documents are the issues of the documents cited in the solicitation. JEDEC INTERNATIONAL (JEDEC) JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington, VA

16、 22201-2107; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the

17、event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements The indi

18、vidual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been grant

19、ed transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the r

20、equirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, co

21、nstruction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as spec

22、ified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91618 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A

23、SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC+125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device types Limits Unit Min Max Input leakage current ILI0.4 V VIH1, 2, 3 All -10 10 A Output low voltage VOLVCC= 4.5 V, IO

24、L= 8.0 mA VIL= 0.8 V, VIH= 2.2 V 1, 2, 3 All 0.4 V Output high voltage VOHVCC= 4.5 V, IOH= -2.0 mA VIL= 0.8 V, VIH= 2.2 V 1, 2, 3 All 2.4 V Operating supply current ICC1f = 15.3 MHz, outputs open 1, 2, 3 All 150 mA VCC= 5.5 V Standby power supply current ICC2R = W = RS = FL / RT = VIH, outputs open

25、1, 2, 3 All 25 mA Power down current ICC3All inputs = VCC- 0.2 V, outputs open, f = 0 MHz 1, 2, 3 All 4.0 mA Input capacitance CINVI= 0 V , f = 1.0 MHz TA= +25C, See 4.3.1c 4 All 10 pF Output capacitance COUTVO= 0 V , f = 1.0 MHz TA= +25C, See 4.3.1c 4 All 10 pF Functional tests See 4.3.1d 7, 8A, 8B

26、 All Shift frequency fSCL= 30 pF See figures 3 and 4 9, 10, 11 01 15 MHz 02 20 Read cycle time tRC9, 10, 11 01 65 ns 02 50 Access time tA9, 10, 11 01 50 ns 02 40 Read recovery time tRR9, 10, 11 01 15 ns 02 10 See footnotes at the end of the table. Provided by IHSNot for ResaleNo reproduction or netw

27、orking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91618 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions -55C TC+125C 4.5 V VCC 5.5

28、V unless otherwise specified Group A subgroups Device types Limits Unit Min Max Read pulse width tRPW1/ CL= 30 pF See figures 3 and 4 9, 10, 11 01 50 ns 02 40 Read pulse low to data bus at low-Z tRLZ 2/ 9, 10, 11 01-04 10 ns 05 5 Write pulse low to data bus at low-Z tWLZ 2/ 3/ 9, 10, 11 01 10 ns 02

29、5 Data valid from read pulse high tDV 9, 10, 11 All 5 ns Read pulse high to data bus high-Z tRHZ 2/ 9, 10, 11 01 30 ns 02 25 Write cycle time tWC9, 10, 11 01 65 ns 02 50 Write pulse width tWPW 1/ 9, 10, 11 01 50 ns 02 40 Write recovery time tWR9, 10, 11 01 15 ns 02 10 Data setup time tDS9, 10, 11 01

30、 30 ns 02 20 Data hold time tDH9, 10, 11 01 5 ns 02 0 Reset cycle time tRSC9, 10, 11 01 65 ns 02 50 Reset pulse width tRS 1/ 9, 10, 11 01 50 ns 02 410 See footnotes at the end of the table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MIC

31、ROCIRCUIT DRAWING SIZE A 5962-91618 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions -55C TC+125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device type

32、s Limits Unit Min Max Reset recovery time tRSR CL= 30 pF See figures 4 and 5 9, 10, 11 01 15 ns 02 10 Reset setup time tRSS9, 10, 11 01 50 ns 02 40 Retransmit cycle time tRTC9, 10, 11 01 65 ns 02 50 Retransmit pulse width tRT 1/ 9, 10, 11 01 50 ns 02 40 Retransmit recovery time tRTR 9, 10, 11 01 15

33、ns 02 10 Reset to empty flag low tEFL9, 10, 11 01 65 ns 02 50 Reset to empty flag and almost empty flag low tRSF19, 10, 11 01 65 ns 02 50 Reset to half full flag and full flag high tRSF29, 10, 11 01 65 ns 02 50 Read low to empty flag low tREF 9, 10, 11 01 45 ns 02 35 Read high to full flag high tRFF

34、 9, 10, 11 01 45 ns 02 35 Read pulse width after EF high tRPE9, 10, 11 01 50 ns 02 40 Write high to empty flag high tWEF9, 10, 11 01 45 ns 02 35 Write low to full flag low tWFF9, 10, 11 01 45 ns 02 35 Write low to half full flag low tWHF9, 10, 11 01 65 ns 02 50 See footnotes at the end of the table.

35、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91618 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continue

36、d. Test Symbol Conditions -55C TC+125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device types Limits Unit Min Max Read high to half-full flag high tRHFCL= 30 pF See figures 3 and 4 9, 10, 11 01 65 ns 02 50 Write pulse width after full flag high tWPF9, 10, 11 01 50 ns 02 40 Read hi

37、gh to transitioning almost empty flag tRF 9, 10, 11 01 65 ns 02 50 Write low to transitioning almost empty flag tWF 9, 10, 11 01 65 ns 02 50 Output enable high to output disable tOEHZ 2/ 9, 10, 11 01 25 ns 02 20 Output enable high to output disable tOELZ 2/ 9, 10, 11 01 25 ns 02 20 Output enable low

38、 to output disable tOELZ 2/ 9, 10, 11 01 25 ns 02 20 Output enable low to data valid tAOE 9, 10, 11 01 25 ns 02 20 XI pulse width tXI 1/9, 10, 11 01 50 ns 02 40 XI recovery time tXIR 9, 10, 11 01 10 ns 02 10 XI set-up time tXIS 9, 10, 11 01 15 ns 02 15 Read/write low to XO low tXOL 9, 10, 11 01 50 n

39、s 02 40 Read/write high to XO high tXOH9, 10, 11 01 50 ns 02 40 1/ Pulse widths less than minimum value are not allowed. 2/ If not tested, shall be guaranteed to the limits specified in table I. 3/ Only applies to read data flow-through mode. Provided by IHSNot for ResaleNo reproduction or networkin

40、g permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91618 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 Device types All Case outlines X Terminal number Terminal symbol 1 VCC2 W 3 D84 D35 D26 D17 D08 XI 9 AEF 10 FF 11 Q0

41、12 Q113 Q214 Q315 Q816 GND 17 GND 18 R 19 Q420 Q521 Q622 Q723 XO / HF 24 EF 25 OE 26 FL / RT 27 NC 28 D729 D630 D531 D432 VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-916

42、18 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 9 DSCC FORM 2234 APR 97 Reset and retransmit Single device configuration/width expansion mode Mode Inputs Internal status Outputs RS RT XI Read Pointer Write Pointer EF FF HF AEF Reset 0 X 0 Location zero Location zero 0 1 1 0

43、 Retransmit 1 0 0 Location zero Unchanged X X X X Read / Write 1 1 0 Increment 1/ Increment 1/ X X X X 1/ Pointer will increment if flag is high. Reset and first load Depth expansion/compound expansion mode 1/ XI is connected to XO of previous device. NOTES: RS = Reset input, FL / RT = First load/re

44、transmit, EF = Empty flag output, FF = Full flag output, XI = Expansion input, and HF = Half-full flag output 0 = Low level voltage 1 = High level voltage X = Dont care FIGURE 2. Truth tables. Inputs Internal status Outputs Mode RS FL XI Read pointer Write pointer EF FF Reset first device 0 0 1/ Loc

45、ation zero Location zero 0 1 Reset all other devices 0 1 1/ Location zero Location zero 0 1 Read / write 1 X 1/ X X X X Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91618 DLA LAND AND MARITIME COLUMBUS, OH

46、IO 43218-3990 REVISION LEVEL A SHEET 10 DSCC FORM 2234 APR 97 NOTE: CLincludes scope and jig capacitance. AC test conditions Input pulse levels GND to 3.0 V Input rise and fall times 5 ns Input timing reference levels 1.5 V Output reference levels 1.5 V FIGURE 3. Output load circuit and ac test cond

47、itions. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91618 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 11 DSCC FORM 2234 APR 97 FIGURE 4. Timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91618 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 12 DSCC FORM 2234 APR 97 FIGURE 4. Timing w