DLA SMD-5962-91641 REV B-2010 MICROCIRCUIT DIGITAL CMOS REAL TIME CLOCK MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to MIL-PRF-38535 requirements. - CFS 05-11-23 Thomas M. Hess B To correct input capacitance (CIN) and output capacitance (COUT) value in table I. Update boilerplate paragraphs to current requirements of MIL-PRF-38535. - MAA 10-

2、05-07 Thomas M. Hess THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV B SHET 15 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Wanda G. Meadows DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECK

3、ED BY Thomas M. Hess COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, CMOS, REAL TIME CLOCK, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-08-18 AMSC N/A

4、 REVISION LEVEL B SIZE A CAGE CODE 67268 5962-91641 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E317-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91641 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3

5、990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected

6、 in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 91641 01 M J X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Devic

7、e class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the

8、 MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 8572 Real time clock 1.2.3 Devi

9、ce class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL

10、-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style J GDIP1-T24 or CDIP2-T24 24 Dual-in-line 1.2.5 Lead finish. The le

11、ad finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91641 DEFENSE SUPPLY CENTER COLUMBUS COLU

12、MBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V to +7.0 V DC input voltage range (VIN) -0.5 V to VCC+ 0.5 V DC output voltage range (VOUT) . -0.5 V to VCC+ 0.5 V Storage temperature range -65C to +150C Lead tempe

13、rature (soldering, 10 seconds) +260C Junction temperature (TJ) +150C Power dissipation (PD) . 500 mW Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA): Board mount 46C/W Socket mount . 52C/W 1.4 Recommended operating conditions. Supply voltage

14、(VCC) 2/ . 4.5 V dc to 5.5 V dc Supply voltage (VBB) (Battery-backed mode) 2/ 2.2 V to VCC 0.4 V DC input or output voltage (VIN, VOUT) . 0.0 V to VCCCase operating temperature range (TC) . -55C to +125C Address hold after read (tRAH) 3 ns (minimum) Address hold after write strobe (tWAH) 3 ns (minim

15、um) Data hold after write strobe (tWDH) . 3 ns (minimum) 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these d

16、ocuments are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic C

17、omponent Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardiz

18、ation Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ For FOSC= 4.194304 or 4.9152

19、 MHz, VBBminimum = 2.8 V. In battery-backed mode, VBB VCC 0.4 V. Single supply mode: Data retention voltage is 2.2 V minimum. In single supply mode (power connected to VCCpin) 4.5 V VCC 5.5 V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD

20、MICROCIRCUIT DRAWING SIZE A 5962-91641 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes preceden

21、ce. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as

22、modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devi

23、ces and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case out

24、lines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Switching waveforms and test circuit. The switching waveforms and test circuit shall

25、 be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating t

26、emperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PI

27、N may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q

28、and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for devi

29、ce class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device clas

30、s M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the

31、manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535

32、or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing i

33、s required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made av

34、ailable onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without

35、 license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91641 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC+125C 4.5 V VCC 5.5 V VPFAIL VIHVBB= 3 V, CL

36、= 100 pF Group A subgroups Device type Limits Unit unless otherwise specified Min Max Input high voltage VIHAll inputs except OSC IN 1, 2, 3 All 2 V OSC IN with external clock VBB 0.1 Input low voltage VILAll inputs except OSC IN 0.8 V OSC IN with external clock 0.1 Output high voltage (excluding OS

37、C OUT) VOHIOH= -20 A, VCC= 4.5 V VCC 0.1 V IOH= -4 mA, VCC= 4.5 V 3.5 Output low voltage (excluding OSC OUT) VOLIOL= 20 A, VCC= 4.5 V 0.1 V IOL= 4 mA, VCC= 4.5 V 0.25 Input leakage current (except OSC IN) IIVIN= VCC, VCC= 5.5 V 1 A VIN= 0 V, VCC= 5.5 V -1 3-state leakage current IOZVOUT= VCC, VCC= 5

38、.5 V 5 A VOUT= 0 V, VCC= 5.5 V -5 Output high leakage current, INTR pin ILKGVOUT= VCC, VCC= 5.5 V, output open drain 15 A VOUT= 0 V, VCC= 5.5 V, output open drain -15 Quiescent current ICCFOSC= 32.768 KHz, VCC= 5.5 V VIN= VCCor GND 2/ 3/ 275 A FOSC= 32.768 KHz, VCC= 5.5 V VIN= VCCor GND 2/ 4/ 1 mA F

39、OSC= 32.768 KHz, VCC= 5.5 V VIN= VIHor VIL2/ 4/ 12 mA FOSC= 4.9152 MHz or 4.194304 MHz VCC= 5.5 V VIN= VCCor GND 2/ 4/ 8 mA FOSC= 4.9152 MHz or 4.194304 MHz VCC= 5.5 V VIN= VIHor VIL2/ 4/ 20 mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted withou

40、t license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91641 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC+125C 4.5 V VCC 5.5 V VPFAIL VI

41、HVBB= 3 V, CL= 100 pF Group A subgroups Device type Limits Unit unless otherwise specified Min Max Quiescent supply current (single supply mode) ICCVCC= 5.5 V, VBB= GND, VIN= VCCor GND, FOSC= 32.768 KHz 2/ 1, 2, 3 All 40 A VCC= 5.5 V, VBB= GND, VIN= VCCor GND, FOSC= 4.9152 MHz or 4.194304 MHz 2/ 7.5

42、 mA Standby mode battery supply current 2/ IBBVCC= 0 V, FOSC= 32.768 KHz 10 A VCC= 0 V, FOSC= 4.9152 MHz 400 Battery supply leakage current IBLKVCC= 5.5 V, 2.2 V VBB 4.0 V 1 -5 1.5 A 2, 3 -5 3.5 Input capacitance CINSee 4.4.1c F = 1 MHz 4 8 pF Output capacitance COUT9 pFFunctional testing See 4.4.1b

43、 VCC= 4.5 V, 5.5 V 7, 8 Address valid prior to read strobe tARSee figure 3. VPFAIL= 3 V 9, 10, 11 20 ns Read strobe width tRWSee figure 3. VPFAIL= 3 V 5/ 80 ns Chip select to data valid time tCDSee figure 3. VPFAIL= 3 V 80 ns Read strobe to data valid time tRD70 Read or chip select to tri-state tDZ6

44、0 ns Chip select hold after read strobe tRCH0 Minimum inactive time between read or write accesses tDS50 ns Address valid before write strobe tAW20 ns Chip select to end of write strobe tCW90 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without

45、license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91641 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC+125C 4.5 V VCC 5.5 V VPFAIL VIHV

46、BB= 3 V, CL= 100 pF Group A subgroups Device type Limits Unit unless otherwise specified Min Max Write strobe width tWWSee figure 3. VPFAIL= 3 V 6/ 9, 10, 11 All 80 ns Data valid to end of write strobe tDWSee figure 3. VPFAIL= 3 V 50 ns Chip select hold after write strobe tWCH0 1/ Unless otherwise s

47、pecified, all testing shall be conducted under worst-case conditions. 2/ OSC IN driven by a signal generator. Contents of test register = 00H and MFO pin not configured as buffered oscillator output. 3/ ICCtested with all power fail circuitry disabled, by setting D7 of interrupt control register 1 t

48、o 0. 4/ ICCtested with all power fail circuitry enabled, by setting D7 of interrupt control register 1 to 1. 5/ Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low. Hence read commences when both signals are low and terminates when either signal returns high. 6/ Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low. Hence write commences when both signals are low and terminates when either signal returns high. P