DLA SMD-5962-91690 REV E-2002 MICROCIRCUIT LINEAR 12-BIT A D CONVERTER WITH MICROPROCESSOR INTERFACE MONOLITHIC SILICON《硅单块 带微处理器界面的12瓦特交直流转换器 直线式微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with N.O.R. 5962-R016-93. 92-11-09 M. A. FRYE B Redrawn with changes. Add device type 04. Add vendor CAGE 33256. 94-09-01 M. A. FRYE C Changes in accordance with N.O.R. 5962-R017-95. 95-01-17 M. A. FRYE D Changes in accordan

2、ce with N.O.R. 5962-R060-95. 95-01-25 M. A. FRYE E Add device type 05 with a temperature range of 55C to +90C. Make limit changes to the +PSS1 test as specified under table I. - ro 02-10-31 R. MONNIN THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV E E E E E E SHEET 15 16 17 1

3、8 19 20 REV STATUS REV E E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY SANDRA ROONEY DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY CHARLES E. BESORE COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR U

4、SE BY ALL DEPARTMENTS APPROVED BY MICHAEL A. FRYE MICROCIRCUIT, LINEAR, 12-BIT A/D CONVERTER WITH MICROPROCESSOR AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-05-14 INTERFACE, MONOLITHIC SILICON AMSC N/A REVISION LEVEL E SIZE A CAGE CODE 67268 5962-91690 SHEET 1 OF 20 DSCC FORM

5、2233 APR 97 5962-E014-03 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91690 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43

6、216-5000 REVISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are refl

7、ected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 91690 01 M X X Federal stock class designator RHA designator (see 1.2.1) Devicetype (see 1.2.2)

8、 Device class designator Caseoutline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices me

9、et the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 674ZA High performance, 1

10、2-bit A/D converter with microprocessor interface and S/H 02 674ZB Medium performance, 12-bit A/D converter with microprocessor interface and S/H 03 674BT 12-bit A/D converter with microprocessor interface 04 674AT 12-bit A/D converter with microprocessor interface 05 674BT 12-bit A/D converter with

11、 microprocessor interface 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B

12、microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Du

13、al-in-line 3 CQCC1-N28 28 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STA

14、NDARD MICROCIRCUIT DRAWING SIZE A 5962-91690 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ VCCto digital common . 0 V dc to +16.5 V dc VEEto digital common 0 V dc to -16.5 V dc 2/ VLOGICto digital common . 0 V

15、 dc to +7 V dc Analog common to digital common: Device types 01, 02, and 04 -0.5 V dc to +1 V dc Device types 03 and 05 1 V dc Control inputs (CE, CS , AO, 12/8, R / C ) to digital common . -0.5 V dc to VLOGIC+ 0.5 V dc Analog inputs (REF IN, BIP OFF, 10 VIN) to analog common . 16.5 V dc 20 VINanalo

16、g input voltage to analog common . 24 V dc VREF OUTIndefinite short to common momentary short to VCCPower dissipation (PD): Device types 01 02, and 04 (TA= +25C) . 1000 mW Device types 03 and 05 (TA= +25C) 470 mW Lead temperature (soldering, 10 seconds) +300C Storage temperature range -65C to +150C

17、Junction temperature (TJ) . +175C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA): Device types 01 and 02 case X 48C/W Device types 03 and 05 case X . 60C/W Device type 04 case X 50C/W Case 3 48C/W 1.4 Recommended operating conditions. Logic su

18、pply voltage (VLOGIC) +4.5 V dc to +5.5 V dc Positive supply voltage (VCC) . +11.4 V dc to +16.5 V dc Negative supply voltage (VEE) -11.4 V dc to -16.5 V dc 2/ Ambient operating temperature range (TA) : Device types 01 04 -55C to +125C Device type 05 -55C to +90C 2. APPLICABLE DOCUMENTS 2.1 Governme

19、nt specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications a

20、nd Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at

21、the maximum levels may degrade performance and affect reliability. 2/ VEEis not required for operation of devices 01, 02, and 04. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91690 DEFENSE SUPPLY CENTER CO

22、LUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Micr

23、ocircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In

24、the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The

25、 individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The ind

26、ividual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 an

27、d herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table

28、shall be as specified on figure 2. 3.2.4 Block diagrams. The block diagrams shall be as specified on figure 3. 3.3 Electrical performance characteristics and post irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post irradiation paramete

29、r limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The par

30、t shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the de

31、vice. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification ma

32、rk for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT

33、DRAWING SIZE A 5962-91690 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C VCC= +15 V, VEE= -15 V, Group A subgroups Device type Limits Unit VLOGIC= +5 V, u

34、nless otherwise specified Min Max Power supply current 2/ from VLOGICILOGICThree-state outputs 1,2,3 01,02,04 +1.0 mA 03,05 +7.0 Power supply current 2/ from VCCICCThree-state outputs 1,2,3 01,02,04 +9.0 mA 03,05 +7.0 Power supply current 2/ from VEEIEEThree-state outputs 1,2,3 03,05 -14 mA Resoluti

35、on 1,2,3 All 12 Bits Integral linearity error ILE Unipolar 10 V span, Bipolar 20 V span 1 All -0.5 +0.5 LSB 2,3 -1.0 +1.0 Differential linearity error (minimum resolution for which no missing codes are guaranteed) DLE 1,2,3 All 12 Bits Unipolar offset voltage error VIO10 V span 1 All -2.0 +2.0 LSB U

36、nipolar offset voltage drift VIO/ T 10 V span, using internal reference 2,3 All -1.0 +1.0 LSB Bipolar zero offset error BZ20 V span 1 01,02,04 -4.0 +4.0 LSB 03,05 -3.0 +3.0 Bipolar zero offset drift BZ/ T 20 V span, using internal reference 2,3 02,03,04,05 -2.0 +2.0 LSB 01 -1.0 +1.0 Gain error AE Bi

37、polar 20 V span 50 resistor from REF OUT to 1 01,02,04 0.3 %FSR REF IN 03,05 0.125 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91690 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS,

38、 OHIO 43216-5000 REVISION LEVEL E SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TA +125C VCC= +15 V, VEE= -15 V, Group A subgroups Device type Limits Unit VLOGIC= +5 V, unless otherwise specified Min Max Gain error drift AE/ T

39、 Bipolar 20 V span, using internal reference 2,3 01 12.5 ppm/C 02,04 25.0 03,05 17.5 Power supply 3/ 4/ sensitivity to VCC+PSS1 1,2,3 01-04 -1.5 +1.5 LSB 05 -1.0 +1.0 Power supply 3/ 5/ sensitivity to VLOGIC+PSS2 1,2,3 All -0.5 +0.5 LSB Power supply 3/ 6/ sensitivity to VEE-PSS3 1,2,3 All -1.0 +1.0

40、LSB Input impedance 2/ ZIN10 V span 1,2,3 01,02,04 3.75 6.25 k 03,05 3.0 7.0 20 V span 01,02,04 15 25 03,05 6 14 Internal reference 7/ voltage VREFIREFOUT= 2 mA 1,2,3 01,02 9.97 10.03 V 03,04,05 9.9 10.1 Logic input high 2/ 8/ voltage (CE, CS , 12/ 8, R/ C, AO) VIHLogic “1” 1,2,3 All +2.0 +5.5 V Log

41、ic input low 2/ 8/ voltage (CE, CS , 12/ 8, R/ C, AO) VILLogic “0” 1,2,3 All -0.5 +0.8 V See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91690 DEFENSE SUPPLY CENTER COLUMBUS COL

42、UMBUS, OHIO 43216-5000 REVISION LEVEL E SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TA +125C VCC= +15 V, VEE= -15 V, Group A subgroups Device type Limits Unit VLOGIC= +5 V, unless otherwise specified Min Max Logic input curr

43、ent 2/ IIN(LOG)0 to +5.5 V input 1,2,3 01,02 +1.0 A 04 -20 +20 0 to +5.0 V input 03,05 -10 +10 Logic low output 2/ voltage (DB11-DB0, STS) VOLLogic “0, ISINK= 1.6 mA 1,2,3 All +0.4 V Logic high output 2/ voltage (DB11-DB0) VOHLogic “1”, ISOURCE= 500 A 1,2,3 All +2.4 V Three-state output leakage curr

44、ent IZHigh-Z state, (DB11- DB0 only), 1,2,3 01,02 -5.0 +5.0 A Vapplied= 5.0 V 03,05 -10 +10 04 -20 +20 Functional tests 2/ See section 4.4.1b 7,8 All Low R/ C pulse width 9/ tHRLSee figure 4 9,10,11 All 50 ns STS delay from R/ C 10/ tDSSee figure 4 9,10,11 01,02,04 200 ns 03,05 225 Data valid after

45、11/ R/ C low tHDRSee figure 4 9,10,11 All 25 ns STS delay after data valid tHSSee figure 4 9,10,11 01,02,04 300 1000 ns 03,05 30 600 High R/ C pulse width 9/ tHRHSee figure 4 9,10,11 All 150 ns Data access time 12/ tDDRSee figure 4 9,10,11 All 150 ns See footnotes at end of table. Provided by IHSNot

46、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91690 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL E SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symb

47、ol Conditions 1/ -55C TA +125C VCC= +15 V, VEE= -15 V, Group A subgroups Device type Limits Unit VLOGIC= +5 V, unless otherwise specified Min Max STS delay from CE 10/ tDSCSee figure 5 1,2,3 01,02 200 ns 03,05 225 CE pulse width 9/ tHECSee figure 5 1,2,3 All 50 ns CS to CE setup tSSCSee figure 5 1,2

48、3 All 50 ns Conversion time 13/ tC8-bit cycle, see figure 5 9,10,11 All 6 10 s 12-bit cycle, see figure 5 9 15 CS low during CE high tHSCSee figure 5 9,10,11 All 50 ns R/ C to CE setup tSRCSee figure 5 9,10,11 All 50 ns R/ C low during CE high tHRCSee figure 5 9,10,11 All 50 ns AOto CE setup tSACSee figure 5 9,10,11 All 0 ns AOvalid during CE high tHACSee figure 5 9,10,11 All 50 ns Access time (from CE) 12/ tDDSee figure 6 9,10,11 All 150 ns Data valid after CE 11/ low tHD9,10,11 01,02,04 25 ns 9,10, 03,05 2