DLA SMD-5962-91695 REV A-2010 MICROCIRCUIT MEMORY DIGITAL CMOS PROGRAMMABLE LOGIC ARRAY (600 GATES) MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Boilerplate update, part of 5 year review. ksr 10-08-23 Charles F. Saffle THE ORIGINAL FIRST PAGE HAS BEEN CHANGED REV SHEET REV A A A A SHEET 15 16 17 18 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14

2、 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Ken Rice THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A APPROVED BY Michael A. Frye MICROCIRCUIT

3、, MEMORY, DIGITAL, CMOS, PROGRAMMABLE LOGIC ARRAY (600 GATES), MONOLITHIC SILICON DRAWING APPROVAL DATE 92-01-15 REVISION LEVEL A SIZE A CAGE CODE 67268 5962-91695 SHEET 1 OF 18 DSCC FORM 2233 APR 97 5962-E412-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr

4、om IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91695 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space ap

5、plication (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962

6、 - 91695 01 M L A | | | | | | | | | | | | | | | | | Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked device

7、s meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s).

8、 The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 610 EE CMOS 600-gate 20 ns programmable array logic 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follow

9、s: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outlin

10、e(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style L CDIP4-T24 or GDIP3-T24 24 dual-in-line package 3 CQCC1-N28 28 Leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or

11、 MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91695 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute

12、 maximum ratings. 1/ 2/ Supply voltage range (VCC) - -0.5 V dc to +7.0 V dc Programming supply voltage (VPP) - -0.5 V dc to +9.5 V dc DC Input voltage (VI) - - -0.5 V dc to VCC+ 0.5 V dc Power dissipation (PD) - 630 mW Storage temperature range - -65C to +150C Junction temperature (TJ) - +200C 3/ Th

13、ermal resistance, junction-to-case (JC) : Cases L and 3 - See MIL-STD-1835 DC supply current, (ICCor ISS) - + 100 mA DC output current, (IO) per pin - + 25 mA Endurance - 100 cycles (minimum) Data retention - 20 years minimum 1.4 Recommended operating conditions. Supply voltage range (VCC) - +4.5 V

14、dc to +5.5 V dc Maximum low level input voltage (VIL) - -0.5 V dc to +0.8 V dc Minimum high level input voltage (VIH) - +2.0 V dc to VCC+ 0.5 V dc Case operating temperature range (TC) - -55C to +125C Input rise time (TR) - 50 ns maximum Input fall time (TF) - 50 ns maximum Clock pins, rise time - 1

15、0 ns maximum Clock pins, fall time - 10 ns maximum 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documen

16、ts are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Compon

17、ent Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Rob

18、bins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. AMERICAN

19、SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr

20、 Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ All voltages referenced to VSS(VSS=ground) unless

21、otherwise specified. 3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROC

22、IRCUIT DRAWING SIZE A 5962-91695 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 ELECTRONICS INDUSTRIES ALLIANCE (EIA) JEDEC Standard EIA/JESD78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association,

23、2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2

24、.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS

25、 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function a

26、s described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as sp

27、ecified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1 . 3.2

28、.3 Truth table(s). The truth table(s) shall be as specified on figure 2 . 3.2.4 Block diagram. The block diagram shall be as specified on figure 3 . 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characte

29、ristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are define

30、d in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ o

31、n the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certific

32、ation mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a

33、QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of

34、compliance submitted to DLA LAND AND MARITIME-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, app

35、endix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo repr

36、oduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91695 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.8 Notification of change for device class M. For device class M, notification to DLA LAND AND

37、 MARITIME-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DLA LAND AND MARITIME, DLA LAND AND MARITIMEs agent, and the acquiring activity reta

38、in the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircu

39、it group number 42 (see MIL-PRF-38535, appendix A). 3.11 Data retention. A data retention stress test shall be completed as part of the vendors reliability monitors. This test shall be done for initial characterization and after any design or process change which may affect data retention. The metho

40、ds and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein, over the full military temperature range. The vendors procedure shall be kept under document control and shall be made available upon request by the preparing or acquiring activity, along

41、with the test data. 3.12 Processing of EEPLDs: All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.12.1 Conditions of the supplied devices: Devices will be supplied in uncharged/neutral state. No provision will be made for supp

42、lying written devices. 3.12.2 Writing of EEPLDs: When specified, devices shall be written in accordance with the procedures and characteristics specified in 4.6. 3.12.3 Clearing of EEPLDs: When specified, devices shall be cleared in accordance with the procedures and characteristics, specified in 4.

43、7. 3.12.4 Verification of state of EEPLDs: When specified, devices shall be verified as either written to the specified pattern or cleared. As a minimum, verification shall consist of performing a read of the entire array to verify that all bits are in the proper state. Any bit that does not verify

44、to be in the proper state shall constitute a device failure and the device shall be removed from the lot or sample. 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manuf

45、acturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening s

46、hall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in) electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein. b. The test circuit shall be maintai