DLA SMD-5962-91772 REV A-2012 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASABLE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated to current boilerplate for 5 year review. lhl 12-06-19 Charles F. Saffle THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV A A A A A A A A SHEET 15 16 17 18 19 20 21 22 REV STATUS REV A A A A A A A A A A A A A A OF

2、 SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rajesh Pithadia DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED B

3、Y Kenneth Rice APPROVED BY Michael Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS UV ERASABLE PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON DRAWING APPROVAL DATE 93-02-01 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-91772 SHEET 1 OF 22 DSCC FORM 2233 APR 97 5962-E336-12 Provided by IHSNot for Resa

4、leNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91772 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisti

5、ng of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.

6、1.2 PIN. The PIN is as shown in the following example: 5962 - 91772 01 M L A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes

7、Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA devi

8、ce. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 MD5AC312 12 Macrocell EPLD 30 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as

9、follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case

10、outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 Dual-in-line package 1/ 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A f

11、or device class M. _ 1/ Lid shall be transparent to permit ultraviolet light erasure. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91772 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHE

12、ET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ Supply voltage range to ground potential (VCC) . -2.0 V dc to +7.0 V dc DC input voltage . -0.5 V dc to VCC +0.5 V 3/ Maximum power dissipation . 1.0 W 4/ Lead temperature (soldering, 10 seconds) +275C Thermal resistance, junction-to-case (

13、JC) . See MIL-STD-1835 Maximum junction temperature (TJ) . +150C Storage temperature range (TSTG) . -65C to +150C Temperature under bias -55C to +125C Programming supply voltage . -2.0 V to 13.5 V Data retention 10 years Endurance . 25 erase/write cycles (minimum) 1.4 Recommended operating condition

14、s. Supply voltage (VCC) +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) . 0.0 V dc Input high voltage (VIH) 2.0 V dc minimum Input low voltage (VIL) 0.8 V dc maximum Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and

15、 handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circ

16、uits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780

17、- Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 2/ Stresses above the absolute maximum rating may cause permanent d

18、amage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ Minimum dc input voltage is -0.5 V. During transitions, inputs may undershoot to -2.0 V for periods less than 20 ns. Maximum dc voltage on output pins is VCC + 0.5 V, which may overshoot

19、to +7.0 V for periods less than 20 ns under no load conditions. 4/ Must withstand the added PD due to short circuit test (e.g., IOS). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91772 DLA LAND AND MARITIM

20、E COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the soli

21、citation. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 78 - IC Latch-Up Test. (Copies of this document are available online at www.jedec.org/ or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201) (Non-Government standards a

22、nd other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the r

23、eferences cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be

24、in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordanc

25、e with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A a

26、nd herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The

27、 truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in screening (see 4.2 herein) or qualification conformance inspection, groups A, or C (see 4.3 herein), the devices shall be programmed by the manufacturer prior to

28、test. A minimum of 50 percent of the total number of cells shall be programmed or at least 25 percent of the total number of cells to any altered item drawing. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.3 Electrical

29、 performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requir

30、ements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Verification of erasure or programmed EPLDs. When specified, devices shall be verified as either programmed (see 4.6 herein) to the specified pat

31、tern or erased (see 4.5 herein). As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.6 Pro

32、cessing options. Since the device is capable of being programmed by either the manufacturer or the user to result in a wide variety of configurations; two processing options are provided for selection in the contract. 3.6.1 Unprogrammed device delivered to the user. All testing shall be verified thr

33、ough group A testing as defined in 3.2.3.1 and table IIA. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRA

34、WING SIZE A 5962-91772 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.6.2 Manufacturer programmed device delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing,

35、shall be satisfied by the manufacturer prior to delivery. 3.7 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

36、 has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.7.1

37、 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.8 Certificate of compliance. For device classes Q and V, a certifi

38、cate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK

39、-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device cla

40、ss M, the requirements of MIL-PRF-38535, appendix A and herein. 3.9 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this d

41、rawing. 3.10 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.11 Verification and review for device class M.

42、 For device class M, DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.12 Microcircuit g

43、roup assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). 3.13 Endurance. A reprogrammability test shall be completed as part of the vendors reliability monitor. This reprogrammability test shall be do

44、ne only for initial characterization and after any design or process changes which may affect the reprogrammability of the device. This test shall consist of 25 program/erase cycles on 25 devices with the following conditions: a. All devices selected for testing shall be programmed in accordance wit

45、h 3.2.3.1 herein. b. Verify pattern (see 3.5). c. Erase (see 3.5). d. Verify pattern erasure (see 3.5). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91772 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 RE

46、VISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C 4.5 V dc VCC 5.5 V dc Group A subgroups Device type Limits Units unless otherwise specified Min Max High level input voltage 2/ VIH 1, 2, 3 All 2.0 VCC + 0.3 3/ V Low

47、 level input voltage 2/ VIL 1, 2, 3 All -0.3 3/ 0.8 V Low level output voltage VOL IOL = 8 mA, VIL = 0.8 V VCC = minimum, VIH = 2.0 V 1, 2, 3 All 0.45 V High level TTL output voltage VOH (TTL) IOH = -4 mA, VIL = 0.8 V VCC = minimum, VIH = 2.0 V 1, 2, 3 All 2.4 V High level CMOS output voltage 3/ VOH

48、 (CMOS) IOH = -2.0 mA 1, 2, 3 All 3.84 V Input leakage current IL VCC = maximum GND VIN VCC 1, 2, 3 All 10 A Three-state output off current 3/ IOZ VCC = maximum GND VOUT VCC 1, 2, 3 All 10 A Output short circuit current 4/ IOS VCC = maximum VOUT = 0.5 V dc 1, 2, 3 All -30 -90 mA VCC supply current 3/ 5/ ICC VCC = maximum VIN = VCC or GND No load, input frequency = 1 MHz Active mode (turbo = off) 1, 2, 3 All 15 mA Standby current 6/ ISB VCC = maximum VIN = VCC or GND Standby mode 1, 2, 3 All 150 A Input capacitance 3/ CIN VIN = 0 V dc; f = 1.0 MHz (see 4.4.1e)