DLA SMD-5962-92026-1992 MICROCIRCUIT DIGITAL CMOS FIXED POINT PROCESSOR MONOLITHIC SILICON《硅单块 定点处理器 互补金属氧化物半导体 数字微型电路》.pdf

1、SMD-59b2-92026 = 999799b 0029370 74T LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV STATUS REV OF SHEETS 123 SHEET PREPARED BY PMIC NIA STAHDARDIZED MILITARY DRAWIaIG THIS DRAWING IS AVAILABLE FOR tiSE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE . 92-10-1 L AMSC N/A I REVISION LEVEL D

2、EFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 MICROCIRCUIT, DIGITAL, CMOS, FIXED POINT PROCESSOR, MONOLITHIC SILICON I SIZE CAGE CODE A I 67268 5962-92026 SHEET 1 OF 36 I )ESC FORM 193 JUL 91 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 5962-E556-92 Provide

3、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-9202b 9999996 0029L9L 686 W STAWDARDIZED MILITARY DUWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 1. SCOPE 1.1 scole. This drawing forms a part of a one part - me part number documentation

4、 system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes 8, CI, and H) and space application (device classes S and VI, and a choice of case wtlinrs and lead finishes are available and are raflected in the Part or Identifying Nuiaber (PIN). Devic

5、e class M microcircuits represent non-JAN class B microcircuits in accordance with 1.2.1 of HIL-STD-8B3, Vrovisions for the use of MIL-STD-883 in conjunction with conpliant non-JAN devices“. available, a choice of Radiation Hardness Assurance (RHAI levels are reflected in the PIN. When SIZE 5962-920

6、26 A REVISION LEVEL SHEET 4 2 1.2 m. The PIN shall be as shown in the following example: - M M 2 X - - I I I - I 5W 92026 - I I I I I I I LO4 Case Devi ce Devi ce II Federal RHA stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) des i gnator (see 1.2.4) (see 1.2.5) /

7、 (see 1.2.3) I Drawing number 1.2.1 RHA designator. Device classes M, B, and S RHA marked devices shall et the MIL-M-38510 specified RHA levels and shall be marked with the appropriate RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-1-38535 specified RHA levels and shall

8、 be marked with the appropriate RHA designator. A dash (-) indicates*a non-RHA device. 1.2.2 Device tvPt(s). The device type(s) shall identify the circuit function as follows: Devi ce type Generic number Circuit function o1 FXP Fixed point processor 1.2.3 Device class designator. The device class de

9、signator shall be a single letter identifying the product assurance level as follows: Device class Device reauiremts documentation M B or S Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of HIL-STD-883 Certification and qualification to MIL-M

10、-38510 Q or V Certification and qualification to HIL-1-38535 The case outline(s) shall be as designated in HIL-STD-1835 and as follows: 1.2.4 Case wtline(s). Outline letter Descriptive designator Terminals Packaqe style 2 See figure 1 220 Ceramic, unformed-ld, chip carrier 1.2.5 Lead finish. The lea

11、d finish shall be as specified in MIL-l4-38510 for classes i, B, ands or MIL-1-38535 for classes 4 and V. Finish letter “X“ shall not be marked on tho microcircuit or its packaging. for use in specifications when lead finishes A, 8, and C are considered acceptable and interchangeable without prefere

12、nce. The “X“ designation is Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-92026 W 9999996 O029392 532 = STANDARD1 ZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 “ I 5962-92026 SIZE A REVISION LEVEL SHEET 3 a I 1.

13、3 Absolute maximum ratinas. I/ Supply voltage range (V . DC output voltage range V DC input voltage range Output voltage range applm to high 2 state Storage temperature range . Lead temperature (soldering, 10 seconds) . . Thermal resi stance, junct ion-to-case , Naximum power dissipation PD) . Baxim

14、um junction temperature (TJ) . . . -0.5 V dc to +7.0 V dc . -0.5 V dc to VDD + 0.5 V dc - 0.5VdctoV +0.5Vdc . -0.5 V dc to VDD + 0.5 V dc . 45C to +150!D . +25OoC .4OC/W . 2.18 . t175C Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-92026 99

15、99796 0029393 Y59 2.2 Non-Government publications. herein. the DOUSS cited in the solicitation. are the issues of the documents cited in the solicitation. The following documentCs) form a part of this document to the extent specified Unless otherwise specified, the issues of documents not listed in

16、the DODISS Unless otherwise specified, the issue of the documents which are DoD adopted are those listed in the issue cf IBM VLSI SYSTEMS, FSD, MANASSAS, VA 155A701 - Engineering and Manufacturing Test Specificdtion. (Applications for copies should be addresses to the International Business Machine

17、Corporation, Federal Sector Division, 9500 Godwin Drive, Manassas, VA 22110.) AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-88 - Standard Guide for the Reasurenwnt of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies should b

18、e addressed to the American Society for Testing and Haterials, 1916 Race Street, Phi ladelphia, PA 19103-1187.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. 3. REQUIREMENTS 3.1 Th

19、e individual item requirements for device class M shall be in accordance with 1.2.1 of MIL-STD-883, “Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices“ and as specified herein. The individual item requirements for device classes B and S shall be ih accordance with M

20、IL-M-38510 and as specified herein. included in this SMD. MIL-1-38535, the device manufacturers Quality Management CQH) plan, and as specified herein. Item requirements. For device classes B and S, a full electrical characterization table for each device type shall be The individual item requirement

21、s for device classes Q and V shall be in accordance with 3.2 Desian, construction, and physical dimensions. The design, construction, and physical dimensions shall be a3 specified in MIL-M-38510 for device classes M, 6, and S and MIL-1-38535 for device classes Q and V and herein. 3.2.1 3.2.2 Termina

22、l connections. Case outline(s1. The case outlineb) shall be in accordance with 1.2.4 herein and figure 1. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagranW. 3.2.4 Switching waveformW and test circuitW. The block diagramCs) shall be as specified on figure 3. The switchi

23、ng waveformW and test circuitCs) shall be as specified on figure 4. 3.2.5 Radiation exriosure circuit. 3.3 Electrical performance characteristics and postirradiation parameter limits. The radiation exposure circuit shall be as specified on figure 5. Unless otherwise specified herein, the electrical

24、performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each

25、 subgroup are defined in tables IA and IB. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. Marking for device class M shall be in - Marking for device classes accordance with MIL-STD-883 (see 3.1 herein). MIL-BL-103. Q and V shall be in accordance with MIL-1-38535. In additi

26、on, the manufacturers PIN may also be marked as listed in Marking for device classes B and S shall be in accordance with MIL-M-38510. STANDARDIZED SIZE 5962-92026 ._ . . MILITARY DRAWING A DEFBNSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET DESC FORM 193A JUL 91 Provided by IHS

27、Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-92026 W 9999996 0029394 395 W STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 SIZE 5962-92026 A REVISION LEVEL SHEET 5 TABLE XA. Electrical performance characteristics. iymb

28、o 1 - OH Conditions -55OC 5 TC 5 +125“C 4.5 V 5 VDD 5 5.5 V 11 subgroup$ unless otherwise specified . 1. 2. 3 Unit Test levice type ts - kX Li - Min High Level (TTL) output voltage All - ALI - All - - 0.6 V VDD = 4.5 V, IOH = -400 PA VIL = 0.8 V, VIH = 2.2 V . - V Low level (TTL) output voltage - Al

29、l - All - All - All - V High level (TTL) input voltage - V Low level (TTL) input voltage - All - IH All - AL 1 - AL1 AL1 - - All - All High level input current 1, 2, 3 VDD = 5.5 v, VIN = 0.0 v I Lou level input current - High level input current (Soft pull-ups) - 5/ See footnotes at end of table. Pr

30、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-72026 = 9999996 0029195 221 m Conditions 4.5 V S VDD I 5.5 V unless otherwise specified- -55OC S TC 5 t125OC I/ Group A subgroup STMDAIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTO

31、N, OHIO 45444 SIZE 5962-92026 A REVISION LEVEL SHEET TABLE IA. Electrical ;Performance characteristics - Continued. Test ievi c( type AL 1 All - - - ALL Lin - Min - - - -1 o 1, 2, 3 Eh- TA = -55C to +12SoC VIN = 0.0 v Lou level input current (soft pull-ups) U - 3/ - 10 1, 2, 3 VDD = 5.5 v, vo = 5.5

32、v VIL = 0.0 V, VIH = 5.0 V High impedance output leakage current All - All fill - - 411 411 - - Al 1 - All Lou impedance output leakage current VDD = 5.5 v, vo = 0.0 v VIL = 0.0 V, VIH = 5.0 V Standby supply current (TTL level 1/01 1, 2, 3 VDD = 5.5 V, f = 0.0 MHz (All other inputs = VIL or VIH) 21

33、Input capacitance s/ Output capacitance s/ Functional tests (LSSD testing) fi/ ill ill - - Ill VDD = 5.0 V *IO percent VINO = 0.0 v “INI = DD (See 4.4.lb) I 9,10,11- Operating frequency I/ IfDD = 4.5 v IfINO = 0.0 v = V See figure 4 Il1 - See footnotes at end of table. DESC FORM 193A JUL 91 Provided

34、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5762-92026 W 999999b 0029396 Lb8 Test TABLE IA. Electrical performance characteristics - Continued. Symbol All All All All All All nil nit 911 N11 411 ill Local processor system bus - tSTUP Input setup dela

35、y, transfer acknowledge 11.6 - 3/ -0.4 I/ 2.4 - 3/ 0.1 - 31 2.8 - 3/ 2.7 - 3/ I Input setup delay, command - 91 - I Input setup delay, data STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I - 9/ SIZE 5962-92026 A REVISION LEVEL SHEET 7 I Input setup delay, data par

36、ity - 9/ * Input setup delay, memory access error I - 1 o/ Input setup delay, memory bus error - 1 o/ See footnotes at end of table. Conditions unless otherwise specified- -55C d TC 5 +125C 4.5 v s VDD = 5.5 v I/ I I Group A Device subgroups I type I+ I I I See figure 4 Unit Provided by IHSNot for R

37、esaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-92026 m 9999996 0029397 OT4 m Test TABLE IA. Electrical Performance characteristics - Continued. Conditions Synibol -55OC S TC 5 +12SoC Group A Device Limits Unit 4.5 V VDD 5 5.5 V 11 subgroups type Min unless otherwi

38、se specified input setup delay, parity Put away bus Input setup delay, acknowledge ns 9,10,11 All -1.5 n D R H tSnp VDD 4.5 V, - 9 All VIN - 0.8 V or VIH See figure 4 - - 21 - 31 - 81 - Input setup delay, address STARDARDIZED MILITARY DRAWING DEFEWSE ELECTROUICS SUPPLY CENTER DAYTON, OHIO 45444 Inpu

39、t setup delay, address parity SIZE 5962-92026 A REVISION LEVEL SHEET 8 Input setup delay, data Input setup delay, data parity aut away control bus - %TUP ns -ee footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-9202b

40、 m 999999b 0029398 T30 Conditions -55OC 5 T .c +125OC 4.5 v s V -5 5.5 v unless otherw!e specified i/ Unit Group A Device Limits subgroups type STANDARDIZED MILITARY DRAWING DEFENSE ELECTROICS SUPPLY CENTER DAYTON, OHIO 45444 SIZE 5962-92026 A REVISION LEVEL SHEET 9 TABLE IA. I_ Processor break poin

41、t ical performance characteristics - Continued. - %TUP 2.8 - 9,10,11 All See figure 4 - 2f - H ns - Input setup delay, instruction SOC Instruct ion bus - %TUP Input setup delay, data = 0.8 V or VI, See figure 4 Operand queue Input setup delay, element select - ns - All I 9,10,11 v = 4.5 v VI; = 0.8

42、V or VIH STUP - All - All - Al 1 - All All - - nil - R11 See figure 4 - a/ ns - ns - ns - Input setup delay, tag Input setup delay, parity Input setup delay, status bus Se! footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SM

43、D-5962-92026 9999996 0029399 977 Test Conditions Symbol -55OC d Tc S t125OC Group A Device Limits Unit 4.5 VI: V S 5.5 V I/ subgroups type Min unless othepwise specified - Arbitration I I I 9,10,11 All Input setup delay, CPU win M D R H tSNP VDD = 4.5 v - 9 All VIN = 0.8 V or VIH See figure 4 - c 11

44、 - a/ Check point retry Input setup delay, processor sync 9,10,11 All 1.7 ns M D R H tsTUp VDD = 4.5 V - 9 Al 1 VIN = 0.8 V or VIH See figure 4 - - 3/ - 2/ - - 8/ Miscellaneous Input setup delay, parity disable 9,10,11 All -0.4 M D R H tSTUp VDD = 4.5 V - 9 AL1 VIN = 0.8 V or VIH See figure 4 - - -

45、21 31 Y See footnotes at end of table. STbloDbRDI ZED MILITARY DEUWIWG DEFENSE ELECTROIPICS SUPPLY CMTKR DbETo#, I0 44444 SIZE 5962-92026 A REVISION LEVEL SHEET DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5762-92026 m 77

46、77776 O027200 417 m Test Conditions unless otherwise specified- Symbo 1 -55C 5 TC I +12SoC Group A Device Limits Unit 4.5 V 5 VDD = 5.5 V I/ subgroups type Local processor system bus Input hold delay, transfer acknowledge STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 4

47、5444 Input hold delay, coinnand SIZE 5962-92026 A REVISION LEVEL SHEET 11 Input hold delay, data - 9/ Input hold delay, data parity Input hold delay, memory access error _. Input hold delay, memory bus error - IO/ See footnotes at end of table. VDD = 4.5 v, VIN = 0.8 V or VIH See figure 4 - 81 pq9 H

48、 - 2/ 9,10,11 2/ ALL ALL All All All ALL All All All All Al 1 - ns - ns - ns - ns ns ns - Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-9202b m 999999b 0029203 355 m TABLE IA. Electrical perfornce characteristics - Continued. _- Conditions

49、 4.5 Y = vCD = 5.5 v Unit Test Cyaibol -55t = T 5 t125C Group A Device Lin! ts- . . unless otherw!sr specified- 11 subgroups typ Put away bus Input hold delay, acknowledge Input hold delay, address Input hold delay, address pari$ Input hold delay, data Input hold delay, data parity Put away control bus sec footnotes at