DLA SMD-5962-92065 REV B-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 64K X 8-BIT REGISTERED PROM MONOLITHIC SILICON《CMOS数字微电路存储器 单片硅 64kx8位注册可编程只读存储器》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Boilerplate update and part of five year review. tcr 06-11-06 Raymond Monnin B Updated Input capacitance (CIN) in Table I from 10 pF to 12 pF. ksr 07-11-02 Robert Heber REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEE

2、T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye AND AGENCIES OF

3、 THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 94-04-08 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 64K X 8-BIT REGISTERED PROM, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-92065 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E057-08 Provided by IHSNot for ResaleNo reproduction or

4、networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92065 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high r

5、eliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. Th

6、e PIN is as shown in the following example: 5962 - 92065 01 Q X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA m

7、arked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Dev

8、ice type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 CY7C287-65 64K x 8-bit registered PROM 65 ns 02 CY7C287-55 64K x 8-bit registered PROM 55 ns 1.2.3 Device class designator. The device class designator is a single let

9、ter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to

10、 MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CDIP3-T28 or GDIP4-T28 28 Dual-in-line Y CQCC1-N32 32 Rectangular chip carrier 1.2.5 Lead finish. The lead finish is as specifie

11、d in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92065 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 RE

12、VISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 3/ Supply voltage range to ground potential (VCC) -0.5 V dc to +7.0 V dc DC voltage range applied to the outputs in the high Z state. -0.5 V dc to +7.0 V dc DC input voltage -3.0 V dc to +7.0 V dc DC program voltage . 13.0 V

13、dc Maximum power dissipation. 1.0 W 4/ Lead temperature (soldering, 10 seconds). +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ). +175C Storage temperature range (TSTG) . -65C to +150C Temperature under bias . -55C to +125C Data retention 10 years, minimu

14、m 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) . 0 V dc Input high voltage range (VIH) 2.0 V dc to VCC+0.5 V dc Input low voltage range (VIL) -3.0 V dc to 0.8 V dc 5/ Case operating temperature range (TC). -55C to +125C

15、2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.

16、 DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS

17、MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4

18、D, Philadelphia, PA 19111-5094.) 3/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 4/ Must withstand the added PDdue to short circuit test; e.g., ISC. 5/ VILnegative undersh

19、oots of -5.0 V dc are allowed with a pulse width 10 ns. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92065 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 A

20、PR 97 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. ELECTRONICS INDUSTRIES ALLIANCE (EIA) JEDEC Standard EIA/JESD

21、 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-00 - Standard Guide for the Measurement of Single Event

22、 Phenomena Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) (Non-Government standards and other publications

23、are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein

24、, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL

25、-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535,

26、appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device c

27、lass M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The truth table for

28、 unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in groups A, B, C, or D (see 4.4), the devices shall be programmed by the manufacturer prior to test with a checkerboard pattern or equivalent (a minimum of 50 percent of the total

29、number of bits programmed) or to any altered item drawing pattern which includes at least 25 percent of the total number of bits programmed. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.3 Electrical performance charac

30、teristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. Provided by IHSNot for ResaleNo reproduction

31、or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92065 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VCC

32、 5.5 V Group A subgroups Device types Limits Unit unless otherwise specified Min Max Output voltage high VOHVCC= 4.5 V, IOH= -2.0 mA 1, 2, 3 All 2.4 V VIH= 2.0 V, VIL= 0.8 V Output voltage low VOLVCC= 4.5 V, IOL = 6 mA 1, 2, 3 All 0.4 V VIH= 2.0 V, VIL= 0.8 V Input high voltage 1/ VIH1, 2, 3 All 2.0

33、 V Input low voltage 1/ VIL1, 2, 3 All 0.8 V Input leakage current IIXVIN= VCC to GND, VCC = 5.5 V 1, 2, 3 All -10 10 A Output leakage current IOZVOUT = VCC to GND, VCC = 5.5 V 1, 2, 3 All -40 40 A Output short circuit ISCVCC= 5.5 V, VOUT = GND 1, 2, 3 All -20 -90 mA current 2/ 3/ Power supply curre

34、nt ICCVCC= 5.5 V, E / E s = VIH 1, 2, 3 All 150 mA VIN= 0 to 3.0 V, f = fmax 4/ Input capacitance 3/ CINVCC= 5.0 V, VIN= 0 TA = + 25C, f = 1.0 MHz 4 All 12 pF see 4.4.1e Output capacitance 3/ COUTVCC= 5.0 V, VOUT = 0 TA = + 25C, f = 1.0 MHz 4 All 10 pF see 4.4.1e Functional tests see 4.4.1c 7, 8A, 8

35、B All Address setup to clock tSASee figures 3 and 4 as 9, 10, 11 01 65 ns high applicable, and note 5/ 02 55 Address hold from clock tHA9, 10, 11 All 0 ns high Clock high to output tCO9, 10, 11 01 25 ns valid 02 20 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networ

36、king permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92065 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Gr

37、oup A subgroups Device types Limits Unit unless otherwise specified Min Max Output valid from E tDOESee figures 3 and 4 as 9, 10, 11 01 25 ns applicable, and note 5/ 02 20 Clock pulse width 3/ tPWC9, 10, 11 01 25 ns 02 20 E s setup to clock high tSEs9, 10, 11 01 18 ns 3/ 6/ 02 15 E s hold from clock

38、 high tHEs9, 10, 11 01 10 ns 3/ 6/ 02 8 Output valid from tCOs9, 10, 11 01 30 ns CLK / E s 3/ 6/ 02 25 Output three state tHZC9, 10, 11 01 30 ns from CLK / E s 3/ 6/ 02 25 Output three state tHZE9, 10, 11 01 25 ns from E 3/ 02 20 1/ These are absolute values with respect to device ground and all ove

39、rshoots and undershoots due to system or tester noise are included. 2/ For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 3/ Tested initially and after any design or process changes that affect that parameter, and theref

40、ore shall be guaranteed to the limits specified in table I. 4/ At f = fmax, address inputs are cycling at the maximum frequency of 1/tSA. 5/ AC tests are performed with input rise and fall times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and the output load

41、in figure 3 (circuits A and B). 6/ Parameter with synchronous E s option. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92065 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET

42、7 DSCC FORM 2234 APR 97 NC = no connection FIGURE 1. Terminal connections. Device types All Case outlines X Y Terminal number Terminal symbol 1 A9A92 A8 83 A7A74 A6 65 A5A56 A4 47 A3A38 A2NC 9 A1A210 A0 111 O0A012 O1GND 13 O2O014 GND O115 O3O216 O4GND 17 O5O318 O6 419 O7O520 E / E s O621 CP GND 22 A

43、15O723 A14E / E s 24 A13CP 25 A12NC 26 A11A1527 A10 1428 VCCA1329 - A1230 - A1131 - A1032 - VCCProvided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92065 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 RE

44、VISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Read modes (see note) NOTE: X can be VILor VIH. FIGURE 2. Truth table. Circuit A Circuit B Output load Output load for tHZCand tHZENOTE: Including scope and jig. (minimum values) Load All device types R1 658 R2 403 FIGURE 3. Output load circuit and test c

45、onditions. Mode E / E s CP Outputs Asynchronous read VILX O7 O0Synchronous read VILVIL/ VIHO7 O0Asynchronous output disable VIHX HIGH Z Synchronous output disable VIHVIL/ VIHHIGH Z AC test conditions Input pulse levels GND to 3.0 V Input rise and fall times 5 ns Input timing reference levels 1.5 V O

46、utput reference levels 1.5 V Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92065 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 FIGURE 4. Switching w

47、aveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92065 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 10 DSCC FORM 2234 APR 97 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked.