DLA SMD-5962-92078 REV J-2008 MICROCIRCUIT HYBRID MEMORY DIGITAL STATIC RANDOM ACCESS MEMORY CMOS 512K x 8-BIT《CMOS 512K x 8-BIT静态随机访问存储器 数字式存储器 混合式微电子电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R109-94. 94-01-25 K. A. Cottongim B Add case outline Y. 94-09-02 K. A. Cottongim C Added device type 09. Made changes to table I. 95-07-19 K. A. Cottongim D Changes in accordance with NOR 5962-R153-97. 96-12-16

2、 K. A. Cottongim E Add case outline T. 97-02-24 K. A. Cottongim F Table I; Changed the max limit for ICCfor device types 06 trough 09 from 200 mA to 210 mA. Changes the max limit for ICCDRfor device types 06 through 09 from 10.4 mA to 12.8 mA. -sld 98-06-23 K. A. Cottongim G Added note to paragraph

3、1.2.2 and table I to regarding the 4 transistor design. Added thermal resistance ratings for all case outlines to paragraph 1.3. Editorial changes throughout. -sld 00-07-03 Raymond Monnin H Table I, tOH, change minimum limit for device types 01 through 03 from 15 ns to 5 ns. 01-04-09 Raymond Monnin

4、J Update drawing to the latest requirements of MIL-PRF-38534. -sld 08-07-08 Robert M. Heber REV SHEET REV J J J J SHEET 15 16 17 18 REV STATUS REV J J J J J J J J J J J J J J OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Steve L. Duncan DEFENSE SUPPLY CENTER COLUMBUS STANDARD

5、 MICROCIRCUIT DRAWING CHECKED BY Michael C. Jones COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Kendall A. Cottongim AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 93-01-25 MICROCIRCUIT, HYBRID, MEMORY, DIGITAL, STA

6、TIC RANDOM ACCESS MEMORY, CMOS, 512K x 8-BIT AMSC N/A REVISION LEVEL J SIZE A CAGE CODE 67268 5962-92078 SHEET 1 OF 18 DSCC FORM 2233 APR 97 5962-E447-08 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92078

7、DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL J SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are r

8、eflected in the Part or Identifying Number (PIN). When available, a choice of radiation hardness assurance levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 - 92078 01 H T X Federal RHA Device Device Case Lead stock class designator type class outline

9、 finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Radiation hardness assurance (RHA) designator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) i

10、ndicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type 1/ Generic number Circuit function Access time 01 WS512K8-120CQ SRAM, 512K x 8-bit 120 ns 02 WS512K8-100CQ SRAM, 512K x 8-bit 100 ns 03 WS512K8-85CQ SRAM, 512K x 8-bit 85 n

11、s 04 WS512K8-70CQ SRAM, 512K x 8-bit 70 ns 05 WS512K8-55CQ SRAM, 512K x 8-bit 55 ns 06 WS512K8-45CQ SRAM, 512K x 8-bit 45 ns 07 WS512K8-35CQ SRAM, 512K x 8-bit 35 ns 08 WS512K8-25CQ SRAM, 512K x 8-bit 25 ns 09 WS512K8-20CQ SRAM, 512K x 8-bit 20 ns 1.2.3 Device class designator. This device class des

12、ignator shall be a single letter identifying the product assurance level. All levels are defined by the requirements of MIL-PRF-38534 and require QML Certification as well as qualification (Class H, K, and E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class D

13、evice performance documentation K Highest reliability class available. This level is intended for use in space applications. H Standard military quality class level. This level is intended for use in applications where non-space high reliability devices are required. G Reduced testing version of the

14、 standard military quality class. This level uses the Class H screening and In-Process Inspections with a possible limited temperature range, manufacturer specified incoming flow, and the manufacturer guarantees (but may not test) periodic and conformance inspections (Group A, B, C, and D). E Design

15、ates devices which are based upon one of the other classes (K, H, or G) with exception(s) taken to the requirements of that class. These exception(s) must be specified in the device acquisition document; therefore the acquisition document should be reviewed to ensure that the exception(s) taken will

16、 not adversely affect system performance. D Manufacturer specified quality class. Quality level is defined by the manufacturers internal, QML certified flow. This product may have a limited temperature range. 1/ Due to the nature of the 4 transistor design of the die in these device types, topologic

17、ally pure testing is important, particularly for high reliability applications. The device manufacturer should be consulted concerning their testing methods and algorithms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING

18、 SIZE A 5962-92078 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL J SHEET 3 DSCC FORM 2234 APR 97 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style T See figure 1 32

19、 Dual-in-line, single cavity X See figure 1 32 Dual-in-line, dual cavity Y 1/ See figure 1 32 Dual-in-line, dual cavity, gull wing leads 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. 2/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc Signa

20、l voltage range (any pin) . -0.5 V dc to +7.0 V dc Power dissipation (PD) . 1 W Thermal resistance, junction- to case (JC): Case outline T 3.113C/W Case outline X . 10C/W Case outline Y 9.76C/W Storage temperature range -65C to +150C Lead temperature (soldering, 10 seconds). +300C 1.4 Recommended op

21、erating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Input low voltage range (VIL) -0.5 V dc to +0.8 V dc Input high voltage range (VIH) +2.2 V dc to VCC+0.3 V dc Output low voltage, maximum (VOL). +0.4 V dc Output high voltage, minimum (VOH) +2.4 V dc Case operating temperature ran

22、ge (TC). -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the so

23、licitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard for Electronic Component Case Outlines. DEPARTMENT OF DEFE

24、NSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia

25、, PA 19111-5094.) 1/ The case outline Y is no longer available. 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking

26、permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92078 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL J SHEET 4 DSCC FORM 2234 APR 97 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited

27、 herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K sh

28、all be in accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 shall include the performance of all tests herein or as designated in the device manufacturers Quality Management (QM) plan or as designated for the applicable device class. The manufacturer may eliminate, modify or optimize the

29、tests and inspections herein, however the performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. In addition, the modification in the QM plan shall not affect the form, fit, or function of the device for the applicable device class. 3.2 Design, constructio

30、n, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specifie

31、d on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. 3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figures 4 and 5. 3.2.5 Block diagram. The block diagram shall be as specified on figure 6. 3.2.6 Output load circuit. The output load cir

32、cuit shall be as specified on figure 7. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full specified operating temperature range. 3.4 Electrical test requirements. The ele

33、ctrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition

34、, the manufacturers vendor similar PIN may also be marked. 3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group

35、A lot sample, for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing act

36、ivity (DSCC-VA) upon request. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this drawing. The certificate of compliance (original copy) submitted to DSCC-VA shall affirm that the manufacturers product meets the performance requ

37、irements of MIL-PRF-38534 and herein. 3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of microcircuits delivered to this drawing. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in acco

38、rdance with MIL-PRF-38534 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDA

39、RD MICROCIRCUIT DRAWING SIZE A 5962-92078 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL J SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions 1/ 2/ -55C TC +125C VSS= 0 V dc +4.5 V dc VCC +5.5 V dc unless otherwise sp

40、ecified Group A subgroups Device types Min Max Unit DC PARAMETERS Operating supply current ICCCS = VIL, OE = VIH, f = 5 MHz, CMOS compatible, VCC = +5.5 V dc 1,2,3 01,02 03 04 05 06-09 70 80 120 165 210 mA Standby current ISBCS = VCC, OE = VIH, f = 5 MHz, CMOS compatible, VCC = +5.5 V dc 1,2,3 01,02

41、 03 04 05 06 07,08 09 2.5 4.0 45 50 55 60 80 mA Input leakage current ILIVCC= +5.5 V dc, VIN= GND or VCC1,2,3 All 15 A Output leakage current ILOCS = VIH, OE = VIH, VOUT= GND or VCC1,2,3 All 15 A Input low voltage VIL 1,2,3 All 0.8 V Input high voltage VIH1,2,3 All 2.2 V Device types 01 through 05,

42、IOL= 2.1 mA Output low voltage VOLDevice types 06 through 09 IOL= 8.0 mA 1,2,3 All0.4 V Device types 01 through 05 IOH= -1.0 mA Output high voltage VOHDevice types 06 through 09 IOH= -4.0 mA 1,2,3 All 2.4 V See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking per

43、mitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92078 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL J SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ 2/ -55C TC +125C V

44、SS= 0 V dc +4.5 V dc VCC +5.5 V dc unless otherwise specified Group A subgroups Device types Min Max Unit DATA RETENTION Data retention supply voltage VDRCS VCC- 0.2 V dc 1,2,3 All 2.0 5.5 V Data retention current 3/ ICCDRVCC= 3.0 V dc 1,2,3 01,02 03 04 05 06-09 1.1 1.6 3.0 10.4 12.8 mA CAPACITANCE

45、01-05 40 Input capacitance 4/ CINVIN=0 V dc, f = 1 MHz 4 06-09 45 pF 01-05 40 Output capacitance 4/ COUTVOUT= 0 V dc, f = 1 MHz 4 06-09 45 pF FUNCTIONAL TESTING Functional tests See 4.3.1c 7,8A,8B All READ CYCLE AC TIMING Read cycle time tRCSee figure 4 9,10,11 01 02 03 04 05 06 07 08 09120 100 85 7

46、0 55 45 35 25 20 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92078 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL J SHEET 7 DSCC FORM 2234 APR 97

47、 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ 2/ -55C TC +125C VSS= 0 V dc +4.5 V dc VCC +5.5 V dc unless otherwise specified Group A subgroups Device types Min Max Unit READ CYCLE AC TIMING - Continued. Address access time tAASee figure 4 9,10,11 01

48、02 03 04 05 06 07 08 09120 100 85 70 55 45 35 25 20 ns Output hold from address change tOHSee figure 4 9,10,11 01-04 05-09 5 3 ns Chip select access time tACSSee figure 4 9,10,11 01 02 03 04 05 06 07 08 09120 100 85 70 55 45 35 25 20 ns Output enable to output valid tOESee figure 4 9,10,11 01,02 0304 05 06 07 08,09 60 55 50 40 35 25 10 ns Chip select to output in low impedance tCLZSee figure 4 9,10,11 01-03 04,05 06-09 10 5