DLA SMD-5962-92122 REV B-1993 MICROCIRCUIT DIGITAL CMOS 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MONOLITHIC SILICON《硅单块 32比特通流误差检测和校正装置 互补金属氧化物半导体 数字微型电路》.pdf

1、P 7 L DESCRIPTION I DATE (YR-MO-DA) SMD-5762-92122 REV B 777777b 0047818 Ob6 W APPROVED LTR A 93-06-11 93-10-12 M. L. Poelking M. L. Poelking Changes in accordance with NOR 5962-11183-93 DRAUING APPROVAL DATE 93-05-07 REVISION LEVEL B Add device type 02. revision. Update boilerplate. Incorporate pre

2、vious NOR SIZE CAGE CODE 5962-92122 A 67268 PREPARED BY Thomas M. Hess PMIC NIA DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 CHECKED BY Thomas M. Hess STANDARDIZED MILITARY DRAWING THIS DRAUING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A MICROCI

3、RCUIT, DIGITAL, CMOS, 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT, MONOLITHIC SILICON APPROVED BY Monica L. Poelking SHEET 1 OF 31 iSC FORM 193 JUL 91 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 5962-E432-93 Provided by IHSNot for ResaleNo reproduction

4、or networking permitted without license from IHS-,-,-SMD-5762-92122 REV B 9999996 0047819 TT2 1. SCOPE 1.1 Scow. This drawing forms a part of a one part - one part mniber docunentation systeni (see 6.6 herein). Tuo product assurance classes consisting of military high reliability (device classes Q a

5、nd M) and space application (device class V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Uhr (PIN). 1.2.1 of MIL-STD-883, I1Provisions for the use of MIL-STO-883 in conjunction uith conpliant non-JAN devices”. available, a choice of Rad

6、iation Hardness Assurance (RHA) levels are reflected in the PIN. Device class M microcircuits represent non-JAN class B microcircuits in accordance uith When 1.2 SIZE 5962-92122 A 5 Parameter 4 IIIIIII name LO 1 2 3 I -SES“Z F SESxZ HIN Propagation delsy from to BEN LM IO SOT OISABLLO E?“ = LOW TO S

7、OWT OISABLEO - LOU TO SOOUT DISABLE0 fa? LOU TO SOOUT DISABLED “IN lo mOUT Px TO PERROUT I xmm: - tPP? I (INPUT I I SOIN TO CEO SLL HIGH TO m CEO? - LOU TO C60 ENABLE ISIIIIIII I tn 1 2 3 4 I 51 32-Bit Configuration Note: Assumes that system data is valid at least 4 ns before SLE goes high FIGURE 3.

8、 Timing waveforms. - lin, oI 1 I I 2 3 4 5 111111 - - HOE MD0 - O31 CB I HLE - SYO m - HERR Parareter Propagation delay name from to I STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 1: il SIZE 5962-92122 A REVISION LEVEL SHEET B 16 II 1 I (SEE NO E) 1 t HIGH TO tl

9、DOuT DISABLED HLE = HIGH TO LOH (SEE NOTEI (SEE NOTEI U tX HLE = HIGH TO XRR = LOH SEE NOTE) (SEE NOTEI U I I t0 1 2 3 4 5 11111 111111 32-Bit Configuration Note: Assumes that memory data and checkbits are valid at least 4 ns before MLE goes high. FIGURE 3. Timing waveforms - Continued. - lin) Max -

10、 MAX HIN HIN HIN HIN HAX HAX HAX HAX MAX HAX MAX MAX MAX Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SND-5962-92L22 REV B 9999996 0047834 209 M STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I I (SEE NOTEI - tP

11、LS I-; I I (SEE NOTEI SIZE A REVISION LEVEL J tHLs (SEE NOTE) I I BESZx t SESZX t CS t MS I tMP LP t PLP BEPZ tSEP 1 1 2 3 4 SI Propagation delay from to = HIGH TO MOouT DISABLED MDIN SET-UP TO MLE = LOW HDIN HOLD TO MLE LOH CHECK611 SET-UP TO MLE = LOU CHECKBIT HOLD TO MLE = LOW - PLEIN LOU TO SD (

12、SEE NO TEP“ LOW TO SDOUT ENABLED C61 TO CORRECTED SDOUT MDIN TO CORRECTED SOOUT HDINTO PARITY OUT HLE HIGH TO PARITY OUT PLE LOU TO PARITY OUT - BEN HIGH TO PARITY OUT SOE LOW TO PARITY OUT - 32-Bit Configuration Note: Assumes that memory data and checkbits are valid at least 4 ns before MLE goes hi

13、gh lin/ Max - MAX MIN MIN MIN HIN MAX MAX MAX MAX MAX MAX MAX MAX MAX MAX MAX - 5962-92122 SHEET 17 DESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-57b2-72L22 REV B 9999976 0047835 i145 - .n/ p11 IIN IAX IIN IAX IAX IAX IAX

14、IAX IAX IAX IAX IAX IAX - 5 Parantar Propagation delay 1111111 name from to BOTH 34 465s STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I*: SLE 3 SIZE 5962-92122 A REVISION LEVEL SHEET B 18 1 1 1 111 SDI SET-UP TO SLEIN m LOL SDIN HOLD TO SLE In LOW PARITY IN I I

15、I -I 3 L INTER-CHIP Px TO m SLE = HIGH TO HoOur MO = LOH TO MDOUT ENABLED - BEN TO HDour SOIN TO CBO SLEIN - HIGH TO CBD ISEE NOTEI m = LOI( TO CBO 1 ENABLED DELAY IDESIGN OEPENDENT 1 PCBI TO CBO I 11111111111 I I I to 1 2 345 these tests shall have been fault graded in accordance with MIL-STD-883,

16、test method 5012 (see 1.5 herein). Subgroup 4(CIN a? COUT) shall be measured only for the initial test and after process or design changes which may affect capacitance. For device classes c. A minim sanple size of 5 devices with zero rejects shall be required. DESC FORM 193A JUL 91 Provided by IHSNo

17、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-92122 REV B 999999b 0047843 211 = STANDARD1 ZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 TABLE II. Electrical test requirements. SIZE 5962-92122 A REVISION LEVEL SHEET B 26 Test req

18、uirements interim electrical parameters (see 4.2) Final electrical parameters (see 4.2) Sroup A test requirements (see 4.4) Sroup B end-point electrical parameters (see 4.4) Group C end-point electrical parameters (see 4.4) Sroup D end-point electrical parameters (see 4.4) ;roup E end-point electric

19、al parameters (see 4.4) Subgroups (in accordance with MIL-STD-883, method 5005, table I) l I f4 IB Is Device Device I Device class class I class I 1,7,9 I - 1/ PDA applies to subgroup 1 and 4 (i.e.,ICCD1, IccD2 only) - 2/ PDA applies to subgroups 1 and 7. 4.4.2 Grow C inswction. The group C inspecti

20、on end-point electrical parameters shall be as specified in table I1 herein. 4.4.2.1 a. Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: Test condition A or D. lhe test circuit shall be maintained by the manufacturer under docunent revision level

21、 control and shall be made available to the preparing or acquiring activity upon request. shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005. The test circuit b. TA = +12SoC, minim. c. Test duration: 1,000 hour

22、s, except as permitted by method 1005 of MIL-STD-883. DESC FORM 93A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-92122 REV B b 0047844 158 STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 4.4.2.2 A

23、dditional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturers QM plan in accordance with MIL-1-38535. manufacturers TRB in accordance with MIL-1-38535 and shall be ma

24、de available to the acquiring or preparing activity upon request. agplleabke, in accordance with the intent specified in test method 15. The test circuit shall be maintained under document revision level control by the device The test circuit shalt specify the inputs, outputs, blases, and puer d13al

25、patlon, SIZE 5962-92122 A REVISION LEVEL SHEET B 27 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (

26、see 3.5 herein). M shall be M and D. RHA levels for device classes Q and V shall be M, D, R, and H and for device class a. b. End-point electrical parameters shall be as specified in table II herein. For device class M, the devices shall be subjected to radiation hardness assured tests as specified

27、in MIL-1-38535, appendix A, for the RHA level being tested. For device classes GI and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-1-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point electrica

28、l parameter limits as defined in table I at TA = +2SC *5C, after exposure, to the subgroups specified in table II herein. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied. c. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging sha

29、ll be in accordance with MIL-STD-883 (see 3.1 herein) for device class M and MIL-1-38535 for device classes Q and V. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logist

30、ics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.1.2 Substitutability. 6.2 Configuration control of SMDs. record for the individual documents. Form 1692, Engineering Change Prop

31、osal. Device classes B and GI devices will replace device class M devices. All proposed changes to existing SMDs will be coordinated with the users of This coordination will be accomplished in accordance with MIL-STD-973 using DD 6.3 Record of users. Military and industrial users shall inform Defens

32、e Electronics Supply Center when a system application requires configuration control and which SMDs are applicable to that system. of users and this list will be used for coordination and distribution of changes to the drawings. covering microelectronic devices (FCC 5962) should contact DESC-EC, tel

33、ephone (513) 296-6047. DESC will maintain a record Users of drawings 6.4 Comments. Comments on this drawing should be directed to DESC-EC, Dayton, Ohio 45444, or telephone (513) 296-5377. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-92I12

34、2 REV B 9999996 0047845 094 vcc 1-10 GND1-12 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined n MIL-1-38535 and MIL-STD-1331. TABLE III. Pin descriptions. Symbol I/O I Name and Function +5 Volts Ground P OutDuts and enables - ERR - HERR

35、 - PERR - O I O - O O O Power supply pins Checkbitsat (00, 01) Partial-checkbits-out (IO) Checkbits-out (11): In a single EDC system, the checkbits are output to the checkbit memory on these outputs. In the lower slice in a cascaded EDC system, the “partial-checkbits“ used by the upper slice are out

36、put by these outputs (generate path only.) “final-checkbits: appear at these outputs (generate path only.) Checkbits ait Enable: Enables checkbit output drivers when low. In the upper slice in a cascade, the Syndmiedit (00) Partial-Syndrome-Out (10) Partial-Checkbits-Out (11): In a 32-bit EDC system

37、, the syndrome bits are output on these pins. 64-bit cascaded system, the “Partial-Syndrome bits appear at these outputs (detect/correct path.) outputs (correct path only.) In a the data is latched when SLE is low. Pipeline latch enable: PLE is an input which controls a pipeline latch, which in turn

38、 controls data to be output on the SD bus and the MUS during byte merges. Use of thic latch is optional. The latch is transparent when PLE is low; the data is latched when PLE is high. System output enable: hen low, enables system output drivers and parity output drivers if corresponding byte enable

39、 inputs are high. Byte enables: In systems using separate 1/0 mry buses, BEn is used to enable the SD and parity outputs for byte n. The BEn pins also control the lbyte corrected or uncorrected data from the memory data latch is directed to the MD 1/0 pins and used for checkbit generation for byte n

40、. during correction cycles. Uhen BEn is low, the data from the system data latch is directed to the MD 1/0 pins and used for checkbit generation for byte n. The latch is - Uhen BEn is high, the This is used in partial-word-write operations or BEo controls SD0-7 BE1 controls SD8-,5 BE2 controls SD16-

41、23 BE3 controls SD,4-31 They also output corrected old data or neu data to be written Ikary data bus: detection and/or correction. to main memory when the EDC unit used in a bi-direction configuration. Memory latch enable: CBI inputs. lhe latch is transparent when MLE is high; data is latched when M

42、LE is low. when identified as the upper slice in a &-bit cascade, the checkbit latch is bypassed. Ikary output enable: Parity /O: respective bytes when that byte is being output on the SD buu These pins also serve as parity inputs and are used in generating the parity error (PERR) signal under certa

43、in conditions (see Byte enable definition.) of the parity select pin (PSEL.) Parity select: If the parity select pin is low, the parity is even. If the parity select pin is high, the parity is odd. These 1/0 pins accept a 32-bit data word from main memory for error MLE is used to latch data from the

44、 HD inputs and checkbits from the - HOE enable memory data bus output drivers when low. The parity 1/0 pins for bytes O to 3. These pins output the parity of their The parity is odd or even depending on the state Inpits I I I Checkbits-in (00) Checkbits-in-1 (10) Partial-syndrome-in (11): In a singl

45、e EDC system or in the lower slice of a cascaded EDC system, these inputs accept the checkbits from the checkbit memory. inputs accept the llpartial-syndranell from the lower slice (Detect/correct path.) In the upper slice in a cascaded EDC system, these Provided by IHSNot for ResaleNo reproduction

46、or networking permitted without license from IHS-,-,-SMD-5962-92222 REV B M 9999996 0047847 967 M STANDARD1 ZED SIZE MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 Symbol I/O Name and Function I Imuts Ccont.) 5962-92122 REVISION LEVEL SHEET B 30 - CLEAR SYNCLK SCLKEN - I l I

47、 - I I I xl 1 x10 O00 xo1 1 O0 - Part id-checkbi ts- in ( 1 O) In a single EDC system, these inputs are unused but should not abe allowed to float. IN a cascaded EDC system, the Ilpartial-checkbitcl1 used by the lower slice are accepted by these inputs (correction path only.) checkbits11 generated b

48、y the lower slice are accepted by these inputs (generate path.) CQ)E identity: (00) Single 32-bit EDC unit (01) &-bit llcheckbit-generate-only* unit Hode select: Selects one of four operating modes. mHomlm d: mGenerate-c&tectm mde: Error generation and detection are normal. mError-dete-aitpitm iode:

49、 Allows the uncorrected data captured from an error event by the error-data register to be read b- system for diagnostic purposes. register is cleared by toggling CLEAR low. record the syndnd and uncorrected data from the first error that occurs after they are reset by the CLEAR pin. there is a positive edge on SYNCLK, an error condition is indicated (ERR = low), and the error counter indicates ze