DLA SMD-5962-92260 REV A-1996 MICROCIRCUIT DIGITAL FAST CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS AND LIMITED OUTPUT VOLTAGE SWING .pdf

1、SMD-5962-92260 REV A 9999996 0090400 462 m DEFENSE LOGISTICS AGENCY DEFENSE SUPPLY CENTER, COLUMBUS POST OFFICE BOX 3990 COLUMBUS, OH 43216-5000 NOV 13 1998 IN REPLY REFER TO DSCC-VAC (Mr. T. Nguyen/(DSN)850-0671/614-692-067 l/tvn) SUBJECT: Notice of Revision (NOR) 5962-R026-97 for Standard Microcir

2、cuit Drawing (SMD) 5962-92260 Mi 1 it ary Andustry Distribution The enclosed NOR is approved for use effective as of the date of the NOR. In accordance with MIL-STD-100 SMD holders should, as a minimum, handwrite those changes described in the NOR to sheet 1 of the subject SMD. After completion, the

3、 NOR should be attached to the subject SMD for future reference. Those companies who were listed as approved sources of supply prior to this action have agreed to actions taken on devices for which they had previously provided DSCC a certificate of compliance. This is evidenced by an existing active

4、 current certificate of compliance on file at DSCC with a DSCC record of verbal coordination. The certificate of compliance for these devices is considered concurrence with the new revision unless DSCC is otherwise notified. If you have comments or questions, please contact Thanh Nguyen at (DSN)850-

5、067 1/(6 14)692-0671. 1 Encl MONICA L. POELKING Chief, Custom Microelectronics Team Federal Recycling Program Printed on Recycled Paper Licensed by Information Handling Services- I“.“ a emwk Redhon P ed 07 add “A. Revisions description column; add “Changes in accordance with NOR 5962-R026-97“. Revis

6、ions date column; add “96-10-17“. Revision level block; add “A“. Rev status of sheets; for sheets 1 and 6, add “A“. Table I, output short circuit current, 10s; change maximum limit from “-225 mA“ to “-250 mA“. Revision level block; add “A“. d. TITLE Chief, Custom Microelectronics Team 15a. ACTIVITY

7、ACCOMPLISHING REVISION DSCC-VAC ID Form 1695. APR 92 Previous editions are obsolete Licensed by Information Handling ServicesLTR DESCRIPTION DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 DATE (YR-MO-DA) APPROVED MICROCIRCUIT, DIGITAL, FAST CMOS, 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH THR

8、EE-STATE OUTPUTS, TTL COMPATIBLE INPUTS AND LIMITED OUTPUT VOLTAGE SWING, MONOLITHIC SILICON PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAUING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A DESC FORM 193 CAGE CODE 5962-92260 IZE A I 67268 I I I PREPARED

9、BY Thanh V. Nguyen CHECKED BY Thanh V. Nguym APPROVED By Monica L. Poelking DRAUING APPROVAL DATE 94-09-22 REVISION LEVEL SHEET 1 OF 18 JUL Y1 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 5962-E41 9-94 Licensed by Information Handling Services1.1 Seope. This draw

10、ing forms a part of a one part - one part number documentaticm system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes Q and MI and space application (device class VI, and a choice of case outlines and lead finishes are available and are reflect

11、ed in the Part or Identifying NuAber (PIN). 1.2.1 of MIL-STD-883, “Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices“. available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. Device class t! microcircuits represent non-JAM class B

12、microcircuits in accordance with Uhen 1.2 M. The PIN shall be as shown in the following example: 1.2.4 Case outlinds). The case outline(s1 shall be as designated in MIL-STD-1835, and as follows: Outline letter Descriptive designator Terminals Package style X GDFPI-F48 48 Flat pack I l 1.2.5 Lead fin

13、ish. The lead finish shall be as specified in MIL-STD-883 (see 3.1 herein) for class M or MIL-1-38535 for classes Q and V. without preference. Finish letter “X“ shall not be marked on the microcircuit or its packaging. The “X“ designation is for use in specifications when lead finishes A, 8, and C a

14、re considered acceptable and interchangeable Sr i 92260 r f 1 1 Federal RHA Devi ce Device Case Lead stock class designator tYPe class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing nunber 1.2.1 RHA desianator. Device class M RHA marked d

15、evices shall nett the MIL-1-38535 appendix A specified RHA levels and shall be ierked with the appropriate RHA designator. NIL-38535 specified RHA levels end shall be marked with the appropriate RHA designator. non-RHA device. Device classes Q and V RHA marked devices shall mt the A dash (-) indicat

16、es a 1.2.2 Device type(s). The device typeCs) shall identify the circuit function as follows: Devi ce type Generic number Circuit function o1 54FCT16374T 16-bit edge-triggered D-type flip-flop with three-state outputs, TTL compatible inputs and limited output voltage swing 02 54F CT16374AT 16-bit ed

17、ge-triggered D-type flip-flop with three-state outputs, TTL compatible inputs and limited output voltage suing 03 54FCT16374CT 16-bit edge-triggered D-type flip-flop with threestate outputs, TTL compatible inputs and limited output voltage swing 1.2.3 Device class desimator. The device class designa

18、tor shall be a single letter identifying the product assurance level as follows: Device class Device requirements documentation R- .:;* Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance vi th 1 -2.1 of MIL-STD-883 Q or V Certification and qualification to

19、MIL-1-38535 STANDARD 5962-92260 MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 91 Licensed by Information Handling Services1 SMD-5962-92260 9999996 0069889 TT7 I Supply voltage range (V - - - - - - - - - - - - - - - - - - DC input voltage range FV ) - -

20、- - - - - - - - - - - - - - - DC output voltage range dN - - - - - - - - - - - - - - - - DC input clamp current (i 3T(v = -0.5 v - - - - - - - - - DC output clamp current (1,) (fiouT -0.5 V and +7.0 V) - - - - DC output source current (I - - - - - - - - - DC output sink current (IOLy(per output) - -

21、 - - - - - - - - Storage teqxrature range (T -_-_-_-_- Case temperature under bias ?fG -) - - - - - - - - - - - - - Lead temperature (soldering, 18%conds) - - - - - - - - - - - Thermal resistance, junction-to-case (eJc) - - - - - - - - - - Junction temperature (TJ) - - - - - - - - - - - - - - - - -

22、- Maximum power dissipation (PD) - - - - - - - - - - - - - - - - 1 (per output) DC V current (Icc) - - - - - - - - - - - - - - - - - - - - Grw$ Current (IGND) - - - - - - - - - - - - - - - - - - - - ! 1.4 Recommended operatinq conditions. 2/ I/ Supply voltage range (Vc ) - - - - - - - - - - - - - -

23、- - - - input voltage range (v ,!i - - - - - - - - - - - - - - - - - - utput voltage range 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Inputs Outputs - I t - btPLZ 0.0 t- PZL 1.5 V VOL + 0.3 v VOL VOH VOH - 0.3 V 1.5 V 2 - wGND FIGURE 5. Switchinq waveforms and test circuit. I I 1 STANDARD MICROCIRCUIT D

24、RAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I I I 5962-92260 c I I I I I REVISION LEVEL SHEET I 13 I I I DESC FORM 193A JUL 91 Licensed by Information Handling ServicesI STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I NPU 1 0.3 V 0.0 v SIZE A 5962

25、-92260 REVISION LEVEL SHEET 14 “ OH 1.5 v OUTPUT 1 %k 101 tSk (O1 OUTPUT 2 - .A. NOTES: 1. When measuring tpLZ and tpZL: VTEST = 7.0 V. 2. When measuring tpHZ, tpZH, tpLH, and tpH : 3. The tpZL and tpLZ reference waveform is #or the output under test with internal conditions such that the output is

26、at VOL except when disabled by the output enable control. output under test with internal conditions such that the output is at Vw except when disabled by the output enable control. CL = 50 pf minimum or equivalent (includes test jig and probe capacitance). RL = 5wR or equivalent. RT = 5M or equival

27、ent. Input signal from pulse generator: shall be measured from 0.3 V to 2.7 V and from 2.7 V to 0.3 V, respectivery; duty cycle = 50 percent. Timing parameters shall be tested at a minimum input frequency of 1 MHz. The outputs are measured one at a time with one transition per measurement. VTEST = o

28、pen. lhe tpZH and tpHZ reference waveform is for the 4. 5. 6. 7. 8. 9. VIN = 0.0 V to 3.0 V; PRR I10 MHz; t 5 2.5 ns; tf 52.5 ns; tr and tf FIGURE 5. Switching waveforms and test circuit - Continued. . Licensed by Information Handling ServicesSMD-5962-92260 W 9999996 0069901 324 W Test requirements

29、Subgroups subgrcnrps (in accordance with (in accordance with HXL-STD-883 , HIL-1-38535, table III) Ttl 5005, table I) Devi ce class H 1 I - I Interim electrical parameters (see 4.2) Devi ce class Q Final electrical parameters (see 4.2) REVISION LEVEL 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, I 7, 8, 9, 10

30、, 11 I 7, a, 9, IO, II Group A test requirements (see 4.4) SHEET 15 1, 2, 3, 4, 5, 6 I Group C end-point electrical I 1, 2, 3, 4, 5, 6 parameters (see 4.4) Group D end-point electricat mrameters (see 4.4) I Group E d-point electrical parameters (see 4.4) 1, 4, 7, 9 I 1, 4, 7, 9 Device class V 1 1, 2

31、, 3, 4, 5, 6 7, a, 9, IO, II 1, 2, 3 1, 4, 7, 9 - I/ - 2/ PDA applies to subgroups 1 and 4 (i.e., ICCT only). PDA applies to subgroups 1, 4, and 7. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall

32、be as specified in the device manufacturers Cw plan in accordance with HIL-1-38535. maintained under document revision level control of the device manufacturers Technology Review Board (TRB) in accordance with HIL-1-38535 and shall be de uvailable to the preparing or acquiring activity upon rquest.

33、The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. Interim and final electrical test parameters shall be as specified in table II herein. Additional screening for device class V beyond the req

34、uirements of device class Q shall be as specified in appendix B of,$IL-I-38535. be in accordance with HIL-1-38535. groups A, 0, C, D, and E inspections (see 4.4.1 through 4.4.4). The burn-in test circuit shali be b. c. 4.3 ualification inspection for device classes Q and V. Qualification inspection

35、for device classes Q and V shall Inspections to be performed shall be those specified in HIL-1-38535 and herein for 4.3.1 Electrostatic discharge sensitivity qualification inspection . testing shall be performed in accordance with HIL-STD-883, method 3015. initial qualification and after process or

36、design changes which my affect ESDS Classification. Electrostatic discharge sensitivity (ESDS) ESDS testing shall be measured only for 4.4 Conformance inspection. Quality conformance inspection for device class H shall be in accordance with HIL-STD-883 (see 3.1 herein) and as specified herein. Inspe

37、ctions to be performed for device class H shall be those specified in method 5005 of HIL-STD-883 and herein for groups A, 6, C, D, and E inspections (see 4.4.1 through 4.4.4). Technology conformance inspection for classes Q and V shall be in accordance with HIL-1-38535 including groups A, 6, C, D, a

38、nd E inspections and as specified herein except where option 2 of HIL-1-38535 permits alternate in-line control test i ng . STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 5962-92260 I DESC FORM 193A JUL 91 Licensed by Information Handling ServicesSMD-59b2-722bO m

39、7797796 0069702 260 m 4.4.1 Group A inspection. SIZE STANDARD A a. b. C. d. 5962-92260 Tests shall be as specified in table II herein. C a#Lt capacitance. CIN and cwl shall be measured between the designated terminal and GND at a frequency Of 1 MHz. and CwT shall be measured only for initial qualifi

40、cation and after process or design changes which may For CIN and CwT, test a 1 applicable pins on five devices with zero failures. a device manufacturer may qualify devices by functional groups. A specific functional group of function types, that by design, will yield the same capacitance values whe

41、n tested in accordance with table I herein. C agTconditions specified herein. guaranteed, if not tested, to the limits and conditions specified in table I herein. shall submit to DESC-EC the device functions listed in each functional group and the test results for each devi ce tested . For device cl

42、ass M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. The test vectors used to verify the truth table shall, at a mininim, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not test

43、ed, to the truth table in figure 2 herein. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device; these tests shall have been fault graded in accordance with MIL-STD-883, test method 5012 (see 1.5 herein). Ground and V initial qualtfication, after proc

44、ess or design changes which MY affect the performance of the device, and any changes to the test fixture. device. All other outputs shalPL& guaranteed, if not tested, to the limits established for the worst case outputs. the worst case package type supplied to this document. All other package types

45、shall be guaranteed, if not tested, to the limits established for the worst case package. determined by the manufacturer. The device manufacturer will submit to DESC-EC &ta that shall include all measured peak values for each device tested and detailed oscilloscope plots for each VoLp, Vo y, VWp, an

46、d YtPoutput under test. Each device manufacturer shall test product on the fixtures they currently use. When a neu fixture is used, the device manufacturer shall inform DESC-EC of this change and test the 5 devices on both the neu and old test fixtures. The device manufacturer shall then submit to D

47、ESC-EC data from testing on both fixtures that shall include all measured peak values for each device tested and detailed oscilloscope plots for each VoLp, VoLv, Vwp, and Vwv from one sample part per function. switching output and the output under test. For VoLp, VoLv, VTP, and VWv, a device manufac

48、turer may qualify devices by functional groups. A specific functional group s all be composed of function types, that by design, will yield the same test values when tested 4n accqdance with table I herein. VoLp, VoLv, VPp, and VWv tests. The device manufacturer nay then test one device function fro

49、m a functional group to the inits and conditions specified herein. All other device functions in that particular functional group shall be guaranteed, if not tested, to the limits and conditions specified in table I herein. device manufacturer shall submit to DESC-EC the device functions listed in each functional grwp and the test results, along with the oscilloscope plots, for each device tested. The device manufacturer shall set a functional group limit for the CI and tests. The device manufacturer may then test one device function from a functional group to the