DLA SMD-5962-92324 REV B-2006 MICROCIRCUIT MEMORY DIGITAL CMOS 8K X 8 NON-VOLATILE STATIC RAM MONOLITHIC SILICON《硅单片 8K X 8非易失性静态随机存取存储器 数字记忆微型电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. Gap 01-05-01 Raymond Monnin B Boilerplate update and part of five year review. tcr 06-05-18 Raymond Monnin REV SHET REV B B B B B B B B SHEET 15 16 17 18 19 20 21 22 REV STATUS

2、 REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Jeff Bowling DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMEN

3、TS APPROVED BY Michael A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 94-02-16 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 8K X 8 NON-VOLATILE STATIC RAM MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-92324 SHEET 1 OF 22 DSCC FORM 2233 APR 97 5962-E461-06

4、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92324 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two pro

5、duct assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (R

6、HA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 92324 01 M X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.

7、2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator.

8、A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Access Store Recall Device type Generic number Circuit function Time Cycle Cycle Endurance 01 11C68 8K X 8 NVSRAM 55 ns 12 ms 25 s 10,000 cycles 02 11C68 8K X 8 NVSRAM 45 ns 12 m

9、s 25 s 10,000 cycles 03 11C68 8K X 8 NVSRAM 35 ns 12 ms 25 s 10,000 cycles 04 11C68 8K X 8 NVSRAM 55 ns 12 ms 25 s 100,000 cycles 05 11C68 8K X 8 NVSRAM 45 ns 12 ms 25 s 100,000 cycles 06 11C68 8K X 8 NVSRAM 35 ns 12 ms 25 s 100,000 cycles 1.2.3 Device class designator. The device class designator i

10、s a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qu

11、alification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CDIP3-T28 or GDIP4-T28 28 Dual -in -line Y CQCC3-N28 28 Rectangular leadless chip carrier 1.2.5 Lead finish. The l

12、ead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92324 DEFENSE SUPPLY CENTER COLUMBUS COL

13、UMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) -0.6 V dc to 7.0 V dc Voltage on DQ (0-7)with outputs in high Z state . -0.5 V to (VCC+ 0.5 V) Input voltage operating range (VIH, VIL) -0.6 V dc to 7.0 V dc Storage t

14、emperature range -65C to +150C Maximum power dissipation (PD) . 1.0 W Maximum output current 15 mA Lead temperature (soldering). 300C Junction temperature (TJ) 3/ 175C Thermal resistance, junction to case (jc): See MIL-STD-1835 Data retention 10 Years to nonvolatile array (minimum) Endurance (as sto

15、re cycles to non-volatile array) Per 1.2.2 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Case operating temperature range (TC) . -55C to +125C Input voltage, low range (VIL) . VSS-0.5 V dc to 0.8 V dc, all inputs Input voltage, high range (VIH) . 2.2 V dc to

16、 VCC+0.5 V dc, all inputs 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the

17、 solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPART

18、MENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700

19、Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may affect reliability. This is a stress rating only, and functional operation of the device at conditions above

20、 those indicated in the operational sections of this specification is not implied. 2/ All voltages are referenced to VSS(ground). 3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Prov

21、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92324 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following documen

22、ts form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. ELECTRONICS INDUSTRIES ALLIANCE (EIA) JEDEC Standard EIA/JESD 78 - IC Latch-Up Test. (Applications for copies should be a

23、ddressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or t

24、hrough libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a s

25、pecific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the Q

26、M plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design,

27、construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal con

28、nections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns cannot be implemented due to test equipment limitations, alt

29、ernate test patterns to accomplish the same results shall be allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing or acquiring activity upon request. For device classes Q and V

30、alternate test patterns shall be under the control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limi

31、ts. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups

32、 specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space

33、 limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MI

34、L-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reprod

35、uction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92324 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance s

36、hall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 here

37、in). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-385

38、35, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change fo

39、r device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquirin

40、g activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall b

41、e in microcircuit group number 41 (see MIL-PRF-38535, appendix A). 3.11 Endurance. A reprogrammability test shall be completed as part of the vendors reliability monitors. This reprogrammability test shall be done for initial characterization and after any design or process changes which may affect

42、the reprogrammability of the device. The methods and procedures may be vendor specific, but shall guarantee the number of program/erase endurance cycles listed in section 1.3 herein over the full military temperature range. The vendors procedure shall be kept under document control and shall be made

43、 available upon request of the acquiring or preparing activity, along with test data. 3.12 Data retention. A data retention stress test shall be completed as part of the vendors reliability monitors. This test shall be done for initial characterization and after any design or process changes which m

44、ay affect data retention. The methods and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military temperature range. The vendors procedure shall be kept under document control and shall be made available upon request of the acqui

45、ring or preparing activity, along with test data. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92324 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97

46、TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V VSS= 0 V, IOUT= 0 mA Group A subgroups Device type Limits Unit unless otherwise specified Min Max Input leakage current IILVCC= 5.5 V 1, 2, 3 All 1 A (any input) VIN= VSSto VCCHigh impedance output

47、IOLVCC= 5.5 V 1, 2, 3 All 5 A leakage current VIN= VSSto VCCInput logic “1“ voltage VIHAll Inputs 1, 2, 3 All 2.2 VCC+.5 V Input logic “0“ voltage VILAll Inputs 1, 2, 3 All VSS-.5 0.8 V Output logic “1“ voltage VOHIOH= -4 mA 1, 2, 3 All 2.4 V Output logic “0“ voltage VOLIOL= 8 mA 1, 2, 3 All 0.4 V V

48、CCcurrent 1/ ICC1Addresses cycling at tAVAV1, 2, 3 01, 04 70 mA 02, 05 75 03, 06 80 VCCcurrent 2/ ICC2CE ( VCC- 0.2V); all other 1, 2, 3 All 50 mA during store cycle inputs VIN 0.2 V or (VCC- 0.2 V) VCCcurrent (standby, ICC3CE VIH; all others cycling 1, 2, 3 01, 04 20 mA cycling TTL input levels) 3/ 02, 05 23 03, 06 27 VCCDC current (standby, ICC4CE (VCC- 0.2 V); all 1, 2, 3 All 2 mA stable CMOS input levels) others VIN 0.2 V or 2/ (VCC- 0.2V) Input capacitance 4/ CINVIN= 0 V 4 All 5 pF TA= 25C, f = 1.0 MHz See 4.4.1e Output capacitance 4/ COUTVOUT= 0 V 4 All