DLA SMD-5962-93020-1995 MICROCIRCUIT DIGITAL FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVER WITH CURRENT LIMITING RESISTORS AND THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS AND LIMITED OUT.pdf

1、SMD-5962-93020 9999996 0083285 434 LTR DESCRIPTION DATE (YR-MO-DA) APPROVED I T SHEET SHEET REV STATUS OF SHEETS PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A SHEET 123 PREPARED BY Thanh V. Nguyen CHECKE

2、D BY Thanh V. Nguyen APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 95-1 1-28 REVISION LEVEL DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 MICROCIRCUIT, DIGITAL, FAST CMOS, OCTAL BIDIRECTIONAL TRANSCEIVER WITH CURRENT OUTPUTS, TTL COMPATIBLE INPUTS AND LIMITED OUTPUT VOLTAGE SWING, MONO

3、LITHIC SILICON LIMITING RESISTORS AND THREE-STATE A 67268 I 5962-93020 I CAGE SHEET 1 OF 18 DESC FORM 193 JUL 94 5962-El 93-96 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from I

4、HS-,-,-SUD-5762-93020 9999996 0081286 370 H STAN DARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 I 1. SCOPE 1.1 m. This drawing forms a part of a one part - one part nunber documentation system (see 6.6 herein). Two product assurance classes consisting of military high re

5、liability (device classes P and M) and space application (device class V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Nunber (PIN). Device class M microcircuits represent non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD

6、-883, I1Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices“. When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 m. The PIN shall be as shown in the following example: I COL9 SIZE A 5962-93020 REVISION LEVEL SHEET 2 sto

7、ck class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) LA (see 1.2.3) V Drawing number 1.2.1 RHA desia nator. Device class M RHA marked devices shall meet the MIL-1-38535 appendix A specified RHA levels and shall be marked with the appropr

8、iate RHA designator. Device classes P and V RHA marked devices shall meet the MIL-1-38535 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-1 indicates a non-RHA device. 1.2.2 Device tvw(a . lhe device typeCs) shall identify the circuit function as follows: pevi

9、ce tm mer ic number Circuit function o1 54FCT2245T Octal bidirectional transceiver with current limiting resistors and three-state outputs, TTL compatible inputs and limited output voltage suing 02 54FCT2245AT Octal bidirectional transceiver with current limiting resistors and three-state outputs, T

10、TL compatible inputs and limited output voltage swing 03 54FCT2245CT Octal bidirectional transceiver with current limiting resistors and three-state outputs, TTL compatible inputs and limited output voltage swing 1.2.3 Device class des imator. The device class designator shall be a single letter ide

11、ntifying the product assurance level as follows: Device class M Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 P or V Certification and qual if ication to MIL- 1-38535 1.2.4 Case outline(s1 . The case outline(s) shall be as des

12、ignated in MIL-STD-1835, and as follows: Outline letter Descrimive designator Terminals Packaae stvle R S 2 GDIPI-T2O or CDIP2-TZ0 20 GDFP2-F20 or CDFP3-FZ0 20 Flat pack Dual - i n- 1 i ne CPCC1 -N20 20 Leadless chip carrier Provided by IHSNot for ResaleNo reproduction or networking permitted withou

13、t license from IHS-,-,-SMD-5762-93020 D 9999996 0081287 207 D SIZE A STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL 1.3 - UUz/ Supply voltage range (V DC input voltage range Fv,) . DC output voltage range (V T) DC input clamp current (I 2 (vIN = -0

14、.5 v . DC output clamp current (1 ) (VwT = -0.5 V and +7.0 V) . DC output source current (YK (per output) . DC output sink current (IoL (per output) DC Vc current (Icc) . Storage temperature range (T ) . Case temperature under bias . Lead temperature (soldering, 1 seconds) . Thermal resistance, junc

15、tion-to-case (eJc) . Junction temperature (TJ) Maxim power dissipation (PD) GrouA current (IGND) 1.4 Recomnened omrat inq conditions. 2/ 2/ Supply voltage range (Vc ) input voltage range (vIN$ Output voltage range (VwT) . Maximum low level input voltage (VIL) Minimm high level input voltage (VI ) Ca

16、se operating temperature range (T! Maximum input rise or fall rate (At/Av): Maximum high level output current (Io ) . Maxim low level output current (IoL! (from VIN = 0.3 V to 2.7 V, 2.7 V to 0.3 VI 1.5 piaita1 Loaic testina for device classes P and V. 5962-93020 SHEET 3 -0.5 V dc to +7.0 V dc -0.5

17、V dc to Vcc + 0.5 V dc -0.5 V dc to Vcc + 0.5 V dc -20 mA i20 mR -30 mA +70 ml t260 mA +550 mA -65C to +150“C -65C to +135C 4, 5, 6 3.2 - 3.4 Outputs open OE DIR = GND Eight bits toggling 5h duty cycle For nonswitching input, VIN = V - f- = 2.5 MHZ or GEE For switching inputs Gss 4, 5, 6 4, 5, 6 11.

18、4 - 10.0 - 12.0 - - - For witching inputs v = 3.4 v INor GND TC +25“C See 4.4.lb 4 PF Input capacitance Input/output 301 2 capacitance 3012 4 4 Low level ground bounce noise V = 3.0 V, VIL = 0.0 V TiH= +25*C See 4.4.ld See figure 4 mV 4 High level Vcc bounce noise 4 mV Al 1 Al 1 - 4 - L Functional t

19、est 3014 VIH.= 2.0 V, VIL = 0.8 V Verify output Vo See 4.4.1 5.5 v - 7, 8 L - See footnotes at end of table. DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-73020 9999996 0081292 674 9 SIZE A STANDARD MICROCIRCUIT DRAWI

20、NG DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL Test and MIL-STD-883 test method 1/ 5962-93020 SHEET 8 Propagation delay time, An to En, Bn to An 3003 Propagation delay time, oupt enable, OE to An or Bn 3003 Propagation delay disable, OE to An or Bn 3003 time, output Propagati

21、on delay time, output enable, DIR to An or Bn 3003 Propagation delay time, output disable, DIR to An or Bn 3003 - Continued. TABLE I. Flectrical mrformance characteristicg - Symbol tPZHIJ 3L1 tPHZ1 and the absolute value of the magnitude, not the sign, is relative to the minim and maxim limits, as a

22、pplicable, listed herein. All devices shall meet or exceed the limits specified in table I at 4.5 V Vcc s 5.5 V. This parameter is guaranteed, if not tested, to the limits specified in table I herein. Three-state output conditions are required. This test may be performed using VIH = 3.0 V. This test

23、 is guaranteed by the IIL and IIH test. Not more than one output should be tested at a time. ICCD may be verified by the following equation: ICCD = where ICCT, Icc (Icc or ICCH in table I), and AI device under test, Wh tested as described in tab? I, herein. The values for DH, NT, fCp, fi, and Ni sha

24、ll be as listed in the test conditions colm for ICCT Output terminals not designated shall be high level logic, low level logic, or open, and AI tests, the output terminals shall be open. When VIH = 3.0 V is used, the test is guaranteed for VIH = 2.0 V. The duration of the test should not exceed one

25、 second. ICCT - Icc - DHNTAICC fcp/2 + fiNi shall be the measured values of these parameters, for the in table I, herein. DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-73020 9999996 OOBL293 500 = STANDARD MICROCIRCUIT

26、 DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 - Continued. TABLE 1. Electrical oerformance characteristics u This test may be perfordeither one input at a time (preferred method) or with all input pins simultaneously at VIN = V using tke alternate test method, the maximum limit is eq

27、ual to the nunber of inputs at a high TTL input level times 2.0 mi; and the preferred method and limits are guaranteed. CCT is calculated as follows: - 2.1 V (alternate method). Classes Q and V shall use the preferred method. When the test is performed ICCT = ICC + DHNTAICC + ICCD(fCp/Z + fiNi) wher

28、e - Quiescent supply current (any IccL or ICCH) :=-Duty cycle for TTL inputs at 3.4 V NT = Nuniber of TTL inputs at 3.4 V AIcc = Quiescent supply current delta, TTL inputs at 3.4 V ICCD-= Dynamic power supply current caused by an input transition pair (HLH or LHL) fCP - Clock frequency for registere

29、d devices (fCp = O for nonregistered devices) fi = input frequency Ni = Nunber of inputs at fi lJ/ This test is required only for group A testing; see 4.4.1 herein. This test is for qualification only. output and are used to measure the magnitude of in8uced noise caused by other simultaneously switc

30、hing outputs. The test is performed on a low noise bench test fixture. with 500U of load resistance and a minim of 50 pF of load capacitance (see figure 4). Only chip capacitors and resistors shall be used. It is suggested, that whenever possible, this distance be kept to less than 0.25 inches. Deco

31、upling capacitors shall be placed in parallel from Vcc to ground. the device manufacturer. The low and high level ground and V a 1 GHz minim bandwidth oscilloscope with a 504 input idince. The device inputs shall be conditioned such that all outputs are at a high nominal VoH Level. The device inputs

32、 shall then be conditioned such that they switch simultaneously and the output under test remains at V other outputs possible are switched from VoH to VOL. VOHy and yOHP are then measured from the nominaPHVoH level to the largest negative and positive peaks, respectively see figure 4). outputs not u

33、nder test switching from VOL to VoH. The device inputs shall be conditioned such that all outputs are at a low nominal VOL level. shall then be conditioned such that they switch simultaneously and the output under test remains at V other outputs possible are switched from VOL to VoH. VoLp and yOLV a

34、re then measured from the nominaPLVoL level to the largest positive and negative peaks, respectively (see figure 4). outputs not under test switching from VoH to VOL. Ground and V bounce tests are performed on a non-switching (quiescent) For the device under test, all outputs shall be loaded The out

35、put load components shall be located as close as possible to the device outputs. The values of these decoupling capacitors shall be determined by bounce noise is measured at the quiet output using as all This is then repeated with the same The device inputs as all This is then repeated with the same

36、 and ground bounce tests were not completed at the date of this drawing. added by revision no more than 90 days from the date of this drawing. The limits for these parameters l;i/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other log

37、ic patterns used for fault detection. minim, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2 herein. sequence as approved by the qualifying activity on qualified devices. propagat

38、ion defiy time limits for Vc = 4.5 V and 5.5 V are guaranteed, if not tested, to the fimits specified in table I, herein. The test vectors used to verify the truth table shall, at a Functional tests shall be performed in For outputs, L 1.5 V, H 2 1.5 V. = 5.5 V are equal to the limits at Vcc = 4.5 V

39、 and guaranteed by testing at V 14/ AC limits at V 4.5 V. Minim For propagation defay tests, all paths must be tested. SIZE A 5962-93020 REVISION LEVEL SHEET 9 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-93020 99999

40、96 O083294 447 Terminal symbol An (n = 1 to 8) Device types Case outlines Terminal Description Side A inputs or three-state outputs 1 2 3 4 5 6 7 8 9 10 Bn (n = 1 to 8) OE DIR - 01, 02, 03 Side B inputs or three-state outputs Output enable control input (active low) Direction control input Terminal

41、symbol SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL DIR AI A2 A3 A4 A5 A6 A7 A8 GND 5962-93020 SHEET 10 R, S, and 2 Terminal nunber 11 12 13 14 15 16 17 18 19 20 Termi na 1 symbol 88 B7 86 85 B4 83 82 BI OE - “cc I Terminal descriptions I I

42、 FIGURE 1. Terminal connection duty cycle = 50 percent; flN 2-1 MHz. b. tr, tf =-3-ns 11.0 ns. 3.0 ns limit may be increased up to 10 ns, as needed, maintaining the 11.0 ns tolerance and guaranteeing the results at 3.0 ns 21.0 ns; skew between any two switching inputs signals (tsk): For monitored ou

43、tputs, the 50n For input signal generators incapable of maintaining these values of tr and tf, the 5 250 ps. FIGURE 4. Ground bounc e load circuit and waveforms. 5962-93020 REVISION LEVEL STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 94 Provide

44、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-93020 H 9999996 0081297 156 OUTPUT DATA INPUT OUTPUT -trt- t-3*o 2.7 V - L - PZL 7 ENABLE CONTROL INPUT b*PLZ /- WVCC 1 -.I STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHI

45、O 45444 OUTPUT OUTPUT SIZE A 5962-93020 REVISION LEVEL SHEET 13 V V L c 0.0 voa3 % I IJ 1.5 V VOL + 0.3 V VOL y- PZH OH VOH - 0.3 V 1.5 v % GND FIGURE 5. Switchino waveforms and test c i rcuit. DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license

46、 from IHS-,-,-SMD-5962-73020 m 999999b 0083298 O92 TO VCC OR GND AS REQUIRED NOTES: 1. RL - 2. 3. PULSE N * A - GENERATOR 4. 5. 6. 7. DEVICE n UNDER TEST 41 8. 9. tTRL Uhen measuring tpLZ and tpZL: Uhen measuring tpHZl tpZHl tpLH# and tpH : The tp is at 6oL except when disabled by the output enable

47、control. The tpZH and tpHZ reference waveform is for the output under test uith internal conditions such that the output is at VoH except when disabled by the output enable control. CL = 50 pF minim or equivalent (includes test jig and probe capacitance). RL = 500n or equivalent. R = 50n or equivale

48、nt. Input signal from pulse generator: VIN 0.0 V to 3.0 V; PRR i 10 MHz; t i 2.5 ns; tf i 2.5 ns; tr and tf shall be measured from 0.3 V to 2.7 V and from 2.7 V to 0.3 VI respectivery; duty cycle = 50 percent. Timing parameters shall be tested at a minimm input frequency of 1 MHz. The outputs are me

49、asured one at a time with one transition per measurement. VTEsT 7.0 V. VTEST = open. and tpLZ reference uaveform is for the output under test uith internal conditions such that the output FIGURE 5. Suitchins uaveforms and test circuit - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 5962-93020 I I- I I REVISION LEVEL I SHEET I I 14 DESC FORM 193A JUL 94 Provided by IH