DLA SMD-5962-93123 REV A-2012 MICROCIRCUIT MEMORY DIGITAL CMOS 2K X 16-BIT STATE MACHINE PROM MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to reflect current requirements. glg 12-10-17 Charles Saffle REV SHEET REV A A A A SHEET 15 16 17 18 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DLA

2、 LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeffery D. Bowling COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS 2K X 16-BIT STATE MACHINE PROM, MONOLITHIC S

3、ILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 93-03-26 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-93123 SHEET 1 OF 18 DSCC FORM 2233 APR 97 5962-E015-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICR

4、OCIRCUIT DRAWING SIZE A 5962-93123 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class

5、V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 93123 01 M X X Federa

6、l stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are mark

7、ed with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follo

8、ws: Device type Generic number 1/ Circuit function Access time 01 2K x 16-bit State machine PROM 15 ns 02 2K x 16-bit State machine PROM 12 ns 03 2K x 16-bit State machine PROM 15 ns 04 2K x 16-bit State machine PROM 12 ns 1.2.3 Device class designator. The device class designator is a single letter

9、 identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MI

10、L-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CDIP3-T28 or GDIP4-T28 28 Dual-in-line package Y GQCC1-J28 28 “J” lead chip carrier Z GQCC1-J28 44 “J” lead chip carrier U CQCC1-N4

11、4 44 Square leadless chip carrier 3 CQCC1-N28 28 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. _ 1/ Generic numbers are also listed on the Standard Microcircuit Drawing Sour

12、ce Bulletin at the end of this document and will also be listed in MIL-HDBK-103. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93123 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3

13、DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ Supply voltage range with respect to ground (VCC)-0.5 V dc to +7.0 V dc DC voltage applied to the outputs in the High Z state -0.5 V dc to +7.0 V dc DC input voltage -3.0 V dc to +7.0 V dc Maximum power dissipation 1.0 W 3/ Lead temperature (sol

14、dering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +150C Storage temperature range . -65C to +150C Temperature under bias -55C to +125C Data retention . 10 years, minimum 1.4 Recommended operating conditions. Supply voltage (VCC) . 4.5 V

15、dc to 5.5 V dc Ground voltage (GND) 0 V dc Input high voltage (VIH) 2.0 V dc to 6.0 V dc Input low voltage (VIL) . -3.0 V dc to 0.8 V dc 4/ Case operating temperature range (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification,

16、 standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specificati

17、on for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copie

18、s of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2/ Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation

19、at the maximum levels may degrade performance and affect reliability. 3/ Must withstand the added PDdue to short circuit test (e.g., IOS). 4/ Negative undershoots of -0.5 V dc are allowed with a pulse width 10 ns. Provided by IHSNot for ResaleNo reproduction or networking permitted without license f

20、rom IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93123 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified,

21、 the issues of the documents are the issues of the documents cited in the solicitation. JEDEC INTERNATIONAL (JEDEC) JEDEC Standard No. 78 - IC Latch-Up Test. (Applications for copies should be addressed to the JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington,

22、VA 22201-2107; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In th

23、e event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The i

24、ndividual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The indiv

25、idual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and

26、herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table sh

27、all be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be specified by an altered item drawing.

28、 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electri

29、cal test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For pa

30、ckages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance

31、 with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as

32、 required in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93123 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.6 Certificate of

33、compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be l

34、isted as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requireme

35、nts of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided w

36、ith each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.

37、3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at

38、the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). 3.11 Processing PROMS. All testing requirements and quality assurance provisions herein, shall b

39、e satisfied by the manufacturer prior to delivery. 3.11.1 Programmability of PROMS. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified by the manufacturer. 3.11.2 Verification of programmed PROMs. When specified, devices shall be v

40、erified as programmed to a specified program. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the

41、 lot. 3.12 Data retention. A data retention stress test shall be completed as part of the vendors reliability monitors. This test shall be done for initial characterization and after any design or process change which may affect data retention. The methods and procedures may be vendor specific, but

42、shall guarantee the number of years listed in section 1.3 herein over the full military temperature range. The vendors procedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with test data. Provided by IHSNot for ResaleNo

43、 reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93123 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5

44、V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Output high voltage VOHVCC= 4.5 V, IOH= -2.0 mA VIN= VIH, VIL1, 2, 3 All 2.4 V Output low voltage VOLVCC= 4.5 V, IOL= 6.0 mA VIN= VIH, VIL1, 2, 3 All 0.4 V Input high voltage 1/ VIH1, 2, 3 All 2.0 V Input low vo

45、ltage 1/ VIL1, 2, 3 All 0.8 V Input leakage current IIXVCC= 5.5 V 1, 2, 3 All -10 +10 A VIN= VCCto GND Output leakage current IOZVCC= 5.5 V, VOUT= GND 1, 2, 3 All -40 +40 A Output short circuit current 2/ 3/ IOSVCC= 5.5 V, VOUT= GND 1, 2, 3 All -20 -90 mA Power supply current ICCVCC= 5.5 V, IOUT= 0

46、mA 4/ 1, 2, 3 All 90 mA Input capacitance CINVCC= 5.5 V, TA= +25C, f = 1 MHz, 4 All 10 pF 3/ VIN= 0 V, see 4.4.1e Output capacitance COUTVCC= 5.5 V, TA= +25C, f = 1 MHz, 4 All 10 pF 3/ VOUT= 0 V, see 4.4.1e Functional tests See 4.4.1c 7, 8A, 8B All Clock period tCPSee figures 3 and 4 5/ 9,10,11 01,0

47、3 15 ns 02,04 12 Clock high tCH9,10,11 01,03 6.5 ns 02,04 5 Clock low tCL9,10,11 01,03 6.5 ns 02,04 5 Address setup to CLK 6/ tAS9,10,11 01,03 4 or 8 ns 02,04 3 or 7 Address hold from CLK tAH9,10,11 01,03 4 or 1 ns 3/ 6/ 02,04 3 or 0 Address setup to CLK tABS9,10,11 01,03 15 ns with input bypassed 0

48、2,04 12 Address hold from CLK tABH9,10,11 All 0 ns with input bypassed 3/ See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93123 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device typ