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本文(DLA SMD-5962-93173 REV A-2013 MICROCIRCUIT MEMORY DIGITAL CMOS 512 X 9 PARALLEL FIFO MONOLITHIC SILICON.pdf)为本站会员(registerpick115)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA SMD-5962-93173 REV A-2013 MICROCIRCUIT MEMORY DIGITAL CMOS 512 X 9 PARALLEL FIFO MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to reflect current requirements. - glg 13-01-24 Charles Saffle REV SHEET REV A A A A A A A A A A A A A SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11

2、12 13 14 PMIC N/A PREPARED BY Tuan Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 512

3、X 9 PARALLEL FIFO, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 93-10-29 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-93173 SHEET 1 OF 27 DSCC FORM 2233 APR 97 5962-E220-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without lic

4、ense from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93173 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and s

5、pace application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following exampl

6、e: 5962 - 93173 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 sp

7、ecified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identif

8、y the circuit function as follows: Device type Generic number 1/ Circuit function Access time 01 7C451 2K x 9 Cascadable Clocked FIFO 30 ns 02 7C451 2K x 9 Cascadable Clocked FIFO 20 ns 03 7C451 2K x 9 Clocked FIFO 14 ns 1.2.3 Device class designator. The device class designator is a single letter i

9、dentifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-

10、PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 32 Dual-in-line Y CQCC1-N32 32 Rectangular leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in M

11、IL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1/ Generic numbers are also listed on the Standard Microcircuit Drawing Source Bulletin at the end of this document and will also be listed in MIL-HDBK-103. Provided by IHSNot for ResaleNo reproduction or networ

12、king permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93173 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ Supply voltage range to ground potential (VCC) -0.5 V dc to +7.0 V dc DC voltage

13、 applied to the outputs in the high Z state -0.5 V dc to +7.0 V dc DC input voltage . -3.0 V dc to +7.0 V dc Maximum power dissipation 0.825 W Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC): Case X 11C/W Case Y See MIL-STD-1835 Junction temperature (TJ) +175

14、C Storage temperature range . -65C to +150C Temperature under bias -55C to +125C 1.4 Recommended operating conditions. Supply voltage (VCC) . +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) 0 V dc Input high voltage (VIH) . 2.2 V dc minimum Input low voltage (VIL) . 0.8 V dc maximum Case

15、 operating temperature range (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents

16、are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component

17、 Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Ave

18、nue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. JEDEC INTERNATION

19、AL (JEDEC) JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the o

20、rganizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes

21、precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect

22、 reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93173 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The in

23、dividual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The indivi

24、dual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and h

25、erein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. The tr

26、uth table shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full c

27、ase operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the

28、manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for d

29、evice classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The complian

30、ce mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein).

31、 For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for th

32、is drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device

33、classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of product (see 6.2 he

34、rein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers fac

35、ility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appen

36、dix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93173 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Te

37、st Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limit Unit unless otherwise specified Min Max Output high voltage VOHVCC= 4.5 V, IOH= -2.0 mA VIN= VIH(Min), VIL(Max) 1, 2, 3 All 2.4 V Output low voltage VOLVCC= 4.5 V, IOL= 8.0 mA VIN= VIH(Min), VIL(Max) 1, 2, 3 All 0

38、.4 V Input high voltage 1/, 2/ VIH1, 2, 3 All 2.2 V Input low voltage 1/, 2/ VIL1, 2, 3 All 0.8 V Input leakage current IIXVCC= Max 1, 2, 3 All -10 +10 A Output leakage current IOZOE VIHVOUT= VSSto VCC1, 2, 3 All -10 +10 A Power supply current 3/ ICC1VCC= 5.5 V, IOUT= 0 mA, 1, 2, 3 01 110 mA VIN= 0

39、to 3.0 V 02 130 03 150 Power supply current 4/ ICC2VCC= 5.5 V, IOUT= 0 mA, VIN= 0 to 3.0 V 1, 2, 3 All 80 mA Standby current 5/ ICC3VCC= 5.5 V, IOUT= 0 mA, All inputs = VCC1, 2, 3 All 30 mA Input capacitance 6/ CINVCC= 5.0 V, T = 25C, f = 1 MHz, (see 4.4.1e) 4 All 10 pF Output capacitance 6/ COUTVCC

40、= 5.0 V, T = 25C, f = 1 MHz (see 4.4.1e) 4 All 12 pF Functional testing 7/ See 4.4.1c 7, 8A, 8B All Write clock cycle tCKWSee figures 4 and 5 9, 10, 11 01 30 ns 8/ 02 20 03 14 Read clock cycle tCKR9, 10, 11 01 30 ns 02 20 03 14 Clock high tCKH9, 10, 11 01 12 ns 02 9 03 6.5 See footnotes at end of ta

41、ble Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93173 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Conti

42、nued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limit Unit unless otherwise specified Min Max Clock low tCKLSee figures 4 and 5 9, 10, 11 01 12 ns 8/ 02 9 03 6.5 Data access time 9/ tA9, 10, 11 01 20 ns 02 15 03 10 Previous output data hold after read high tO

43、H9, 10, 11 All 0 ns Previous flag hold after read/write high tFH9, 10, 11 All 0 ns Data set-up tSD9, 10, 11 01 12 ns 02 9 03 7 Data hold tHD9, 10, 11 All 0 ns Enable set-up tSEN9, 10, 11 01 12 ns 02 9 03 7 Enable hold tHEN9, 10, 11 All 0 ns OE low to output data valid tOE9, 10, 11 01 20 ns 10/ 02 15

44、 03 10 OE low to output data in low Z 6/, 10/ tOLZ9, 10, 11 All 0 ns OE high to output data in tOHZ9, 10, 11 01 20 ns high Z 6/, 11/, 12/ 02 15 03 10 Read high to parity tPG9, 10, 11 01 20 ns generation 02 15 03 10 Read high to parity error tPE9, 10, 11 01 20 ns flag 02 15 03 10 Flag Delay tFD9, 10,

45、 11 01 20 ns 02 15 03 10 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93173 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TAB

46、LE I. Electrical performance characteristics - continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limit Unit unless otherwise specified Min Max Opposite clock after clock 13/ tSKEW1See figures 4 and 5 8/ 9,10,11 All 0 ns Opposite clock before clock tSKEW29,

47、10,11 01 30 ns 14/ 02 20 03 14 Master preset pulse width tPMR9,10,11 01 30 ns ( MR low) 02 20 03 14 Last valid clock low set-up to MR low tSCMR9,10,11 All 0 ns Data hold from MR low tOHMR9,10,11 All 0 ns Master reset recovery (MR tMRR9,10,11 01 30 ns high set-up to first 02 20 enabled write/read) 03

48、 14 MR high to flags valid tMRF9,10,11 01 30 ns 02 20 03 14 MR high to data outputs low tAMR9,10,11 01 30 ns 02 20 03 14 Program mode - MR low tSMRP9,10,11 01 30 ns set-up 02 20 03 14 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93173 DLA LAND AND MARITIME COL

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