DLA SMD-5962-94744 REV B-1996 MICROCIRCUIT DIGITAL FAST CMOS 16-BIT REGISTERED LATCH TRANSCEIVER WITH PARITY SERIES RESISTOR AND THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS AND LIMITT.pdf

1、 - SMD-5962-94744 REV B = 9999996 0090892 O70 _. I b DEFENSE LOGISTICS AGENCY DEFENSE SUPPLY CENTER, COLUMBUS POST OFFICE BOX 3990 COLUMBUS, OH 43216-5000 IN REPLY REFER TO DSCC-VAC (Mr. T. Nguyen/(DSN)850-0671/6 14-692-0671/tvn) DEC06 1996 SUBJECT: Notice of Revision (NOR) 5962-R055-97 for Standard

2、 Microcircuit Drawing (SMD) 5962-94744 MilitaryAndustry Distribution The enclosed NOR is approved for use effective as of the date of the NOR. In accordance with MIL-STD- 1 O0 SMD holders should, as a minimum, handwrite those changes described in the NOR to sheet 1 of the subject SMD. After completi

3、on, the NOR should be attached to the subject SMD for future reference. Those companies who were listed as approved sources of supply prior to this action have agreed to actions taken on devices for which they had previously provided DSCC a certificate of compliance. This is evidenced by an existing

4、 active current certificate of compliance on file at DSCC with a DSCC record of verbal coordination. The certificate of compliance for these devices is considered concurrence with the new revision unless DSCC is otherwise notified. If you have comments or questions, please contact Thanh Nguyen at (D

5、SN)850-0671/(614)692-0671. 1 Encl Chief, Custom Microelectronics Team Federal Recycling Program Printed on Recycled Paper Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-NOTICE OF REVISION (NOR) THIS REVISION DESCRIBED BELOW HAS BEEN AUTHORIZED FOR T

6、HE DOCUMENT LISTED. ublic repotting burden forthis ccilection is estimated to average 2 hours per response including the tim forrewewing instnictions searching existing dala soums lamerin and maintainin the da$ needed and completing and hewing the mea0;i of i Send cuwwms regardin this burden estimat

7、e or any othei or Information perations%t%ls 128 ,derson Daws Hi hway, Suite 1204. Arlington. VA 22202-4362, and to the ORce of Managemenl and Budget, a erwork Reduction Pmed 070Oltk3) Washington DC 2050% SSUING CONTRACTING OFFICER FOR THE CONTRACT/ PROCURING ACTIVITY NUMBER LISTED IN ITEM 2 OF THIS

8、 FORM. ispect d this cliecon din indidin sug esonsfFreduang this burden, to Dstof Defense Washingtion add “B. Revisions description column: add “Changes in accordance with NOR 5962-R055-97“. Revisions date column; add “96-1 1-08. Revision level block; change from “A to “B. Rev status of sheets; for

9、sheet 1, change from “A to “6“. For sheet 6, add “B. 8. DOCUMENT NO. 596284744 Table I, output short circuit current, 10s; change maximum limit from “-225 mA“ to “-250 mA“. Table I, output drive current, 10; delete this test completely. Revision level block; add “B. I I 3. TITLE OF DOCUMENT MICROCIR

10、CUIT, DIGITAL, FAST CMOS, 16-BIT REGISTEREDILATCH 1 O. REVISION LElTER TRANSCEIVER WITH PARITY, SERIES RESISTOR AND THREE-STATE OUTPUTS, lTL COMPATIBLE INPUTS AND LIMITED OUTPUT VOLTAGE a. CURRENT b. NEW SWING, MONOLITHIC SILICON A B 11. ECP NO. N/A (2) Revised document must be received before manuf

11、acturer may incorporate this change. U a. X (1) Existing document supplemented by the NOR may be used in manufacture. b. ACTIVITY AUTHORIZED TO APPROVE CHANGE FOR GOVERNMENT I d. TITLE I e. SIGNATURE I f. DATE SIGNED I c. TYPED NAME (First, Middle Initial, Last) Chief, Custom Microelectronics Team 1

12、5a. ACTIVITY ACCOMPLISHING REVISION DSCC-VAC I I I DD Form 1695, APR 92 Previous editions are obsolete. (YYMMDD) Monica L. Poelking 96-1 1-08 b. REVISION COMPLETED (Signature) C. DATE SIGNED (YYMMDD) Thanh V. Nguyen 96-1 1-08 Provided by IHSNot for ResaleNo reproduction or networking permitted witho

13、ut license from IHS-,-,-m 9999996 0068306 523 m DEFENSE LOGISTICS AGENCY DEFENSE ELECTRONICS SUPPLY CENTER DAYTON. OH 45444-5765 IN REPLY REFER TO DESC-ELDC (Mr. Nguyen/(AV 986) 5 13-296-6023hvn) SUBJECT: Notice of Revision (NOR) 5962-R093-95 for Standardized Military Drawing (SMD) 5962-94744 Milita

14、ry/Industry Distribution The enclosed NOR is approved for use effective as of the date of the NOR. In accordance with MIL-STD-100 SMD holders should, as a minimum, handwrite those changes described in the NOR to sheet 1 of the subject SMD. After completion, the NOR should be attached to the subject

15、SMD for future reference. Those companies who were listed as approved sources of supply prior to this action have agreed to actions taken on devices for which they had previously provided DESC a certificate of compliance. This is evidenced by an existing active current certificate of compliance on f

16、ile at DESC along with a DESC record of verbal coordination. The certificate of compliance for these devices is considered concurrence with the new revision unless DESC is otherwise notified. If you have comments or questions, please contact Thanh Nguyen at (AV)986-6023 or (513)296-6023. 1 Encl MONI

17、CA L. POELKING Chief, Custom Microelectronics Branch Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-9999996 OOb307 4bT 4. ORIGINATOR a. TYPED NAME (First, Riddle Initial, Last) NOTICE OF REVISION (NOR) b. ADDRESS (Street, City, State, Zip Code) 5. C

18、AGE CODE Defense Electronics Supply Center 67268 1507 Wilmington Pike Dayton, OH 45444-5765 7. CAGE CODE 67268 1. DATE I (YYMMDD) 9. TITLE OF DOCUMENT MICROCIRCUIT, DIGITAL, FACT CMOS, 16-BIT REGISTERED/LATCHED TRANSCEIVEH i.iiTH PAiIITY, SERIES RESiSTOR AND THREE-STATE OUTPUTS, 1TL COFIPATIBLE INPU

19、TS AND LIMITED OUTPUT VOLTAGE SWING, MONOLITHIC SILICON 95-04-04 Th - revi-:osi ,;*:5rt-:S2 i belci !ias been authorized for the document listed. - IO. REVISION LETTER a. CURRENT b. NEW Ini tia1 A a. (X one) X (1) Existing document supplemented by the NOR may be used in manufacture. Form Approved OM

20、B NO. 0704-0188 b. ACTIVITY AUTHORIZED TO APPROVE CHANGE FOR GOVERNMENT 2. PROCURING ACTIVITY NO. c. TYPED NAME (First, Middle Initial, Last) 3. DODAAC d. TITLE Chief, Custom Microelectronics 15a. ACTIViTY ACCO!IFLISHIIIG REVISION DESC-ELDC 6. NOR NO. 5962-RG93-95 8. DOCUMENT NO. 5962-94744 e. SIGNA

21、TURE f. DATE SIGNED (YYMMDD) Monica L. Poelking 95-04-04 b. REVISION COMPLETED (Signature) c. DATE SIGNED ( Y Y MM D D ) Thanh V. Nguyen 95-04-04 11. ECP NO. N/A 13. DESCRIPTION OF REVISION Sheet 1: Revisions ltr column; add “A“. Revisions description column; add “Changes in accordance with NOR 5962

22、-R093-95“. Revisions date column; add “95-04-041. Revision level block; add “A“. Rev status of sheets; for sheets 1 and 7, add “A“. Table I, output current low (I/O pins), IoDL; change maximum limit from “150 mA“ to “200 mA“. Table I, output current high (1/0 pins), IODH; change maximum limit from “

23、-150 mA“ to “-200 mA“ Revision level block; add “A“. Sheet 7: DD Fori 16Y5, APR 92 Previous editions are obsolete Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DATE (YR-MO-DA) LTR DESCRIPTION APPROVED REV STATUS OF SHEETS REV SHEET PMIC N/A 15 16 1

24、7 STANDARD MICROCIRCUIT DRAWING SIZE A THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CAGE CODE 5962-94744 67268 AMSC N/A =-+ SHEET PREPARED BY Thanh V. Nguyen CHECKED BY Thanh V. Nguyen APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 94-10-06 REV

25、ISION LEVEL DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 MICROCIRCUIT, DIGITAL, FAST CMOS, 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY, SERIES TTL COMPATIBLE INPUTS AND LIMITED OUTPUT VOLTAGE SWING, MONOLITHIC SILICON RESISTOR AND THREE-STATE OUTPUTS, ESC FORM 193 JUL 91 DISTRIBUTION S

26、TATEMENT A. Approved for public release; distribution is unlimited. 5962-E420-94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- - b 0068309 232 I- - 1. SCOPE 1.1 Scope. This drawing forms a part of a one part - one part number documentation system

27、(see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes Q and M) and space application (device class VI, and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). 1.2.1 of MIL-STD-883, “Pro

28、visions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices“. available, a choice of Radiation Hardness Assurance (RHA) Levels are reflected in the PIN. Device class i4 microcircuits represent non-JAN class B microcircuits in accordance with Uhen 1.2 m. The PIN shall be as shown

29、 in the following example: 5r 1 94744 i i i Federa 1 RHA Devi ce Device tese Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) I (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device class M RHA marked devices shali meet t

30、he MIL-1-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. MIL-1-38535 specified RHA levels and shall be marked with the appropriate RHA designator. non-RHA device. Device classes Q and V RHA marked devices shall meet the A dash (-) indicates a 1.2.2 Devi

31、ce typeCs). The device type(s1 shall identify the circuit function as follows: Device type Generic number Circuit function o1 54FCT16251 IAT %-bit registered/latched transceiver with parity, series resistor and three-state outputs, TTL compatible inputs and limited output voltage suing 02 54FCT16251

32、1CT 16-bit registered/latched transceiver with parity, series resistor and three-state outputs, TTL compatible inputs and limited output voltage swing 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class

33、Device requirements documentation M Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-CTD-883 Q or V Certification and qualification to MIL-1-38535 1.2.4 Case outline(s). The case outlinecs) shall be as designated in MIL-STD-1835, and as

34、follows: Package style Outline letter Descriptive desiqnator Termi na 1s X GDFPl-FS6 56 Flat pack 1.2.5 Lead finish. The lead finish shall be as specified in MIL-STD-883 (see 3.1 herein) for class M or MIL-1-38535 for classes Q and V. designation is for use in specifications when lead finishes A, 8,

35、 and C are considered acceptable and interchangeable without preference. Finish letter “X“ shalt not be marked on the microcircuit or its packaging. The “X“ STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 5962-94744 I LEVEL I SHEET2 DESC FORM 193A JUL 91 Provided b

36、y IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- 9h O068330 T54 H STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I 1.3 Absolute maximum ratings. 11 2/ 31 SIZE A 5962-94744 REVISION LEVEL SHEET 3 Supply voltage range - - - -

37、- - - - - - - - - - - - - Maximum Lou level input voltage (VIL) - - - - - - - - - - - - Minimum high level input voltage (VI 1 - - - - - - - - - - - - Case operating temperature range (T B - - - - - - - - - - - - Maximum input rise or fall rate (AtSAV): - - - - - - - - Maximum high level output curr

38、ent (I/O pins) (IOH) - - - - - - Maximum low level output current (IoL): (from VIN = 0.3 V to 2.7 V, 2.7 V to 0.3 V) 110 pins - - - - - - - - - - - - - - - - - - - - - - - - - - Open drain pins - - - - - - - - - - - - - - - - - - - - - - 1.5 Digital loqic testing for device classes Q and V. +4.5 V d

39、c to t5.5 V dc +O.O V dc to Vcc +O.O V dc to Vcc 2.0 v -55C to +125C 0.8 v 2.5 ns1V -16 RIA 16 mh 48mA Fault coverage measurement of manufacturing Logic tests (MIL-STD-883, test method 5012) - - - - - - - - XX percent / I 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, bulletin, and

40、 handbook. Unless otherwise specified, the following specification, standards, bulletin, and handbook of the issue listed in that issue of the Department of Defense Index of Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified herein. DESC F

41、ORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SPECIFICATION HILITARY MIL-1-38535 - STANDARDS MILITARY MIL-STD-883 - MIL-STD-973 - MIL-STD-1835 - BULLETIN MILITARY MIL-BUL-IO3 - HANDBOOK MILITARY HIL-HDBK-780 - STANDARD MICROCIRCUIT

42、DRAWING Integrated Circuits, Manufacturing, General Specification for. SIZE A 5962-94744 Test Hethads and Procedures for Microelectronics. Configuration Hanagement. Microcircuit Case Outlines List of Standardized Military Drawings (SMDs) Standardized Mi li tary Drawings. (Copies of the specification

43、, standards, bulletin, and handbook required by manufacturers in connection with Specific acquisition functions should be obtained from the contracting activity or as directed by the contracting activity.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the r

44、eferences cited herein, the text of this drawing shall take precedence. 3. REQUIREMENTS 3.1 The individual item requirements for device class M shall be in accordance with 1.2.1 of MIL-STD-883, “Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices“ and as Specified her

45、ein. device manufacturers Quality Management (QMI plan, and as specified herein. Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-1-38535, the 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimen

46、sions shall be as specified in MIL-STD-883 (see 3.1 herein) for device class !I and MIL-1-38535 for device classes Q and V and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. 3.2.3 Truth tables. 3.2.4 Logic diagram. 3.2.5 Ground boun

47、ce load circuit and waveforms. The terminal connections shall be as specified on figure 1. The truth tables shall be as specified on figure 2. The logic diagram shall be as specified on figure 3. The ground bounce load circuit and waveforms shall be as specified on figure 4. 3.2.6 Switching waveform

48、s and test circuit. The switching waveforms and test circuit shall be as specified on figure 5. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as s

49、pecified in table I and shall apply over the full case operating temperature range. and limits are as specified in table 1. Test conditions for these specified characteristics 3.4 Electrical test requirements. The electricat test requirements shall be the subgroups specified in table 11. The electrical tests for each subgroup are defined in table 1. DEFENSE ELECTRONICS SUPPLY CENTER